Hi Jeff, The m_axis_data_tdata and s_axis_data_tdata signals carry the CHDR packet's data (usually SC16 samples) only. The tuser signals are for the CHDR header. For instance, the incoming CHDR packet's header is output on m_axis_data_tuser (regardless of the state of SIMPLE_MODE). When SIMPLE_MODE=0, the header on s_axis_data_tuser will be used for the outgoing CHDR packet's header. When SIMPLE_MODE=1, the header is handled automatically by reusing the incoming packet's header. Technically, SIMPLE_MODE works by storing the incoming packet's header in a FIFO. That is why when using SIMPLE_MODE you must produce a packet for every packet consumed, otherwise the FIFO will either overflow or underflow.
Jonathon On Wed, Dec 16, 2020 at 6:50 PM Hodges, Jeff <jeff.hod...@gtri.gatech.edu> wrote: > When SIMPLE_MODE=0 for AXI_WRAPPER, is the header provided as the first > data word (or two data words if the timestamp is used) on > m_axis_data_tdata? It seemed redundant since it’s provided on > m_axis_data_tuser, but the Header is shown in the waveform on Slide 22 of > the RFNOC Workshop (Part 2), so I wanted to clarify exactly what the data > on m_axis_data_tdata will be. Also, I assume that this same behavior > should be mimicked on s_axis_data_tdata when sending a packet out, but > again, I wanted to clarify. > > > Thanks, > > > Jeff > ------------------------------ > *From:* Jonathon Pendlum <jonathon.pend...@ettus.com> > *Sent:* Wednesday, December 16, 2020 12:05:58 AM > *To:* Hodges, Jeff > *Cc:* usrp-users@lists.ettus.com > *Subject:* Re: [USRP-users] RFNoC passing metadata on the dataplane > > Hi Jeff, > > Is there a document describing the CHDR header for 3.15? Looking at the >> code, there are significant differences between the header format in 3.15 >> and what’s in the 4.0 spec. I think I understand it from the code, but if >> there’s a doc with more detail or explanation, that would be useful. > > > The RFNoC3 CHDR header is described in the UHD 3.15 manual: > https://files.ettus.com/manual_archive/v3.15.0.0/html/page_rtp.html. > There is a bit more detail in these slides: > https://kb.ettus.com/images/f/f6/rfnoc3_workshop_slides_202008_part_2.pdf > > Is there a maximum payload size for a CHDR data packet > > > Technically it is 64k bytes, but due to FIFO sizing in our devices, you > should not exceed 7992 bytes / 1998 SC16 samples. > > Jonathon > > On Tue, Dec 15, 2020 at 11:18 PM Hodges, Jeff <jeff.hod...@gtri.gatech.edu> > wrote: > >> Thanks, Jonathan, that is very helpful. Two questions using SIMPLE_MODE=0 >> and AXI wrapper: >> >> 1. Is there a document describing the CHDR header for 3.15? >> Looking at the code, there are significant differences between the header >> format in 3.15 and what’s in the 4.0 spec. I think I understand it from >> the code, but if there’s a doc with more detail or explanation, that would >> be useful. >> 2. Is there a maximum payload size for a CHDR data packet >> >> Jeff >> >> ------------------------------ >> *From:* Jonathon Pendlum <jonathon.pend...@ettus.com> >> *Sent:* Friday, December 11, 2020 4:47:57 PM >> *To:* Hodges, Jeff >> *Cc:* usrp-users@lists.ettus.com >> *Subject:* Re: [USRP-users] RFNoC passing metadata on the dataplane >> >> Hi Jeff, >> >> RFNoC3 / UHD 3.15 does not support metadata. That is a new feature in >> RFNoC4 / UHD 4.0, so option 2 is not possible. >> >> If you want to send out metadata in RFNoC3, I would suggest prepending it >> to packets you send to AXI wrapper. You can still use SIMPLE_MODE as long >> as you are producing a packet for every packet consumed. The different >> input/output packet lengths do not matter as AXI wrapper internally >> calculates the output packet length and updates the header automatically. >> >> Jonathon >> >> On Fri, Dec 11, 2020 at 3:48 PM Hodges, Jeff via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> I meant rfnoc_create_verilog.py >>> >>> >>> >>> https://github.com/EttusResearch/uhd/blob/master/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py >>> >>> >>> jeff >>> ------------------------------ >>> *From:* Hodges, Jeff >>> *Sent:* Friday, December 11, 2020 3:44:41 PM >>> *To:* usrp-users@lists.ettus.com >>> *Subject:* RFNoC passing metadata on the dataplane >>> >>> >>> I'd like to pass metadata over the dataplane using the available space >>> in the CHDR header. However, I cannot find an easy way to do this using >>> UHD3.15. >>> >>> >>> I've identified two possible approaches but I'm not sure either will >>> work: >>> (1) Set AXI_Wrapper (Simple_Mode =0) to require user provided CHDR >>> header. It's unclear how to provide the header, and if this can be modified >>> quickly. >>> >>> (2) Expose the AXI-Stream CHDR interface the way UHD4.0 does it: >>> >>> In UHD4.0 the verilog_image_builder.py includes the options to expose >>> HDL interface: >>> >>> o Definition: Which HDL interface to expose >>> o Options: “AXI-Stream CHDR” (axis_chdr), “AXI-Stream Payload Context” >>> (axis_pyld_ctxt), or “AXI-Stream Data” (axis_data) >>> >>> If Option (2) is the recommended, can I just copy the code from >>> verilog_image_builder.py TEMPLATE such as below, or were other changes made >>> to make it incompatible with 3.15? >>> >>> %if config['data']['fpga_iface'] == >>> "axis_pyld_ctxt": >>> assign axis_data_clk = >>> ${config['data']['clk_domain']}_clk; >>> assign axis_data_rst = >>> ${config['data']['clk_domain']}_rst; >>> <%include >>> file="/modules/axis_pyld_ctxt_modules_template.mako"/> >>> >>> >>> >>> Thanks, >>> >>> Jeff >>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>
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