Finally, I mention that, I found there is a bug in UHD 4.1.0.5 or UHD
4.2.0.0 when I used rfnocmodtool to create a rfnoc block:
In a file block.yml file there is a section you should edit...
You should instead ${fpga_lib_dir} add the address rfnoc module folder, For
me this folder is not in UHD RFNOC block folder and I was faced with error
not found...
> makefile_srcs:
> "${fpga_lib_dir}/blocks/rfnoc_block_correlate/Makefile.srcs"
On Sun, Feb 13, 2022 at 10:39 AM sp h <stackprogra...@gmail.com> wrote:
> Finally, I edited the RFNOC image core when I used the default RFNOC
> image core x300_rfnoc_image_core.yml, and run below command,
> I could successfully open UHD project in GUI vivado. Thanks very much
> make X300_HG GUI=1
>
> On Thu, Feb 3, 2022 at 12:13 PM sp h <stackprogra...@gmail.com> wrote:
>
>> I reformed my previous post, I used this command, so when I want to build
>> with GUI=1 option I was faced with some errors
>> make X300_HG GUI=1
>> but when I want to make without GUI=1 option I have not any eros... how
>> can solve this problem?
>>
>> On Mon, Jan 31, 2022 at 2:40 PM sp h <stackprogra...@gmail.com> wrote:
>>
>>> when I want to build an FPGA source for x300 (In Ubuntu 20.04, Gnuradio
>>> 3.8.1, uhd-4.1.0.5) I used the below command:
>>>
>>> source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado
>>> make X300_HG
>>>
>>> But I have been faced with these errors... can any idea for solving this
>>> problem?
>>>
>>> [00:00:23] Starting Synthesis Command
>>> ERROR: [Synth 8-439] module 'rfnoc_block_fft' not found
>>> [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_rfnoc_image_core.v:1354]
>>> ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_image_core'
>>> [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_rfnoc_image_core.v:24]
>>> ERROR: [Synth 8-6156] failed synthesizing module 'bus_int'
>>> [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/bus_int.v:9]
>>> ERROR: [Synth 8-6156] failed synthesizing module 'x300_core'
>>> [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_core.v:9]
>>> ERROR: [Synth 8-6156] failed synthesizing module 'x300'
>>> [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300.v:20]
>>> ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
>>> console or run log file for details
>>> [00:03:31] Current task: Synthesis +++ Current Phase: Starting
>>> [00:03:31] Current task: Synthesis +++ Current Phase: Finished
>>> [00:03:31] Process terminated. Status: Failure
>>>
>>> ========================================================
>>> Warnings: 357
>>> Critical Warnings: 1
>>> Errors: 6
>>>
>>> make[1]: *** [Makefile.x300.inc:127: bin] Error 1
>>> make[1]: Leaving directory
>>> '/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300'
>>> make: *** [Makefile:90: X300_HG] Error 2
>>>
>>>
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