On Wed, Sep 14, 2022 at 1:55 PM Kevin Williams <zs1...@gmail.com> wrote:
> Thanks Brian. I think the core gets generated in a way which respects > back-pressure, so unless a TREADY is seen the core does not generate output > samples. I have observed this by simulating the core in isolation. > On 14 Sep 2022, 17:49 +0200, Brian Padalino <bpadal...@gmail.com>, wrote: > > I believe the AXI spec says that data should be presented when valid, and > the tready signal just accepts that data. You can't rely on tready to be > asserted before asserting tvalid. > > With that being said, I have no idea if this is the source of any of your > issues. > > Brian > > I don't quite understand what you said. To copy from the AXI protocol spec ( https://documentation-service.arm.com/static/60d5b244677cf7536a55c23e?token=) section 2.2: "A Transmitter is not permitted to wait until TREADY is asserted before asserting TVALID. Once TVALID is asserted, it must remain asserted until the handshake occurs. A Receiver is permitted to wait for TVALID to be asserted before asserting TREADY. It is permitted that a Receiver asserts and deasserts TREADY without TVALID being asserted." Waiting for TREADY to be asserted is invalid as a transmitter. Is something not compliant and causing deadlock? Brian
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