Hello everyone,
I am trying to make use of axi_ram_fifo together with a rfnoc block of my own.
Basically, my block receives 2 inputs (one from outside and one from FIFO) and
sends 2 outputs (one to outside and one toFIFO) . These are converted to the
payload and function of my block is to store the data my block receives from a
specific value and receives them later from FIFO after some time. I had thought
the control by means of the valid of sending to FIFO and the ready of reception
from FIFO. However, when I synthesize and execute, I do not receive any data
and checking I have realized that I do not receive any ready (when I am going
to send) nor any valid (when I am going to receive) from the axi_ram_fifo
block.
I don't know if the error is in the conversion from chdr to payload because, I
get the ready from the context but I really don't know.
In my e320 synthesis file I have the connections like this:
Memory characteristics are: 64 mem_data, 31 addres and 1 port.
`# MioRAM0 to fifo0(0)`
` - { srcblk: MioRAM0, srcport: out_1, dstblk: fifo0, dstport: in_0 }`
` - { srcblk: fifo0, srcport: out_0, dstblk: MioRAM0, dstport: in_1 }`
` # Custom block connection: ep4 to MioRAM0 and MioRAM0 to ep4`
` - { srcblk: ep2, srcport: out0, dstblk: MioRAM0, dstport: in_0 }`
` - { srcblk: MioRAM0, srcport: out_0, dstblk: ep2, dstport: in0 }`
` `
` - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram
}`
Thanks in advance.
Adrian CR
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