Hello,
I managed to receive the respective values of m_ready and s_valid. The
problem I think was that I was doing a conversion to chdr-payload and I was
not receiving data. Now I have done a chdr to chdr data and I am receiving
the expected values of these flags. Now I have the problem of how to create
the chdr data. I don't know if any of the 64 bits has to have a special
value. I have seen several schemes but I am not clear about the scheme.
Thanks in advance
Adrian
El vie, 28 oct 2022 16:03, Wade Fife <wade.f...@ettus.com> escribió:
> You mentioned you don't receive any ready. Do you mean that the tready
> signal never asserts on your output port? It is not allowed in AXI-Stream
> to wait for tready to assert before asserting tvalid. Some devices will
> assert tready before tvalid asserts, but some won't. You need to assert
> tvalid when you have data to send. The receiving device will assert tready
> when it is ready to accept data.
>
> You also said that you do not receive any valid. I assume you mean that
> tvalid never asserts on your input port. That would indicate that no data
> is making it to your block. That could be a software issue, or perhaps
> something wrong in your YAML file or your block's code. Perhaps a missing
> clock connection?
>
> Wade
>
> On Thu, Oct 27, 2022 at 6:58 AM <adri96r...@gmail.com> wrote:
>
>> Hello everyone,
>>
>> I am trying to make use of axi_ram_fifo together with a rfnoc block of my
>> own. Basically, my block receives 2 inputs (one from outside and one from
>> FIFO) and sends 2 outputs (one to outside and one toFIFO) . These are
>> converted to the payload and function of my block is to store the data my
>> block receives from a specific value and receives them later from FIFO
>> after some time. I had thought the control by means of the valid of sending
>> to FIFO and the ready of reception from FIFO. However, when I synthesize
>> and execute, I do not receive any data and checking I have realized that I
>> do not receive any ready (when I am going to send) nor any valid (when I am
>> going to receive) from the axi_ram_fifo block.
>>
>> I don't know if the error is in the conversion from chdr to payload
>> because, I get the ready from the context but I really don't know.
>>
>> In my e320 synthesis file I have the connections like this:
>>
>> Memory characteristics are: 64 mem_data, 31 addres and 1 port.
>>
>> # MioRAM0 to fifo0(0)
>>
>> - { srcblk: MioRAM0, srcport: out_1, dstblk: fifo0, dstport: in_0 }
>>
>> - { srcblk: fifo0, srcport: out_0, dstblk: MioRAM0, dstport: in_1 }
>>
>> # Custom block connection: ep4 to MioRAM0 and MioRAM0 to ep4
>>
>> - { srcblk: ep2, srcport: out0, dstblk: MioRAM0, dstport: in_0 }
>>
>> - { srcblk: MioRAM0, srcport: out_0, dstblk: ep2, dstport: in0 }
>>
>>
>>
>> - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport:
>> dram }
>>
>>
>> Thanks in advance.
>>
>>
>> Adrian CR
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>
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