Hi Rob, I believe the underlying code that implements this is here:
https://github.com/EttusResearch/uhd/blob/c354764c93b49c90be08958f942b9bcb7704cbd5/fpga/usrp3/lib/control/simple_spi_core.v#L182 It looks like the clock is inverted every divider+1 cycles, meaning divider+1 is half the SPI clock period, not the full period. If so, the frequency of the SPI clock would actually be (Radio_Clk / (divider + 1)) / 2. That seems to agree with what you're seeing? Just to confirm, can you share the URL for the documentation with this equation? Wade On Wed, Jun 25, 2025 at 4:25 PM Rob Kossler via USRP-users < [email protected]> wrote: > Hi, > The equation in the UHD manual for the X410 SPI clock rate is: > SPI_clk = Radio_clk / (divider + 1) > However, I'm seeing half of that rate if I use the function: > Radio_clk = usrp->get_radio_control()->get_rate(); > Note that this returns the sample rate. I'm wondering if maybe the radio > clock rate is half of the sample rate because it processes multiple samples > per clock cycle. > > So, basically, my question is: what function or functions should I call to > determine the Radio clock rate needed for the equation above? Or is the > equation wrong? > > Thanks. > Rob > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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