Yes, you're right. The clock in this case is 245.76 MHz, but the divider sets the duration of half the SPI clock period, so the equation in your case would be 122.88 MHz / (divider + 1). I agree, the manual deserves some additional explanation. I'll see that it gets updated.
Thanks for reporting this. Wade On Fri, Jun 27, 2025 at 10:26 AM Rob Kossler <[email protected]> wrote: > But, wouldn't your previous comment apply regarding the logic inverting > the spi clock every (divider+1) clock cycles such that a full spi clock > cycle would consume 2*(divider+1) radio clock cycles? If so, then this > explains what I see and the only issue is that the equation in the manual > needs modified by a factor of 2 and perhaps some additional info added > regarding how the user would know what the underlying clock rate is (is it > the master_clock, the radio_clock, etc.). > > If this is not the case, I can open an issue. BTW, I am using UHD 4.8. > Rob > > On Fri, Jun 27, 2025 at 11:17 AM Wade Fife <[email protected]> wrote: > >> Rob, >> >> I don't know why you're seeing that behavior. The radio_clk does actually >> run at 122.88 MHz in your case but the clock driving the SPI controller is >> twice that rate, so I would expect it to result in SPI_clk = 245.76 MHz / >> (divider + 1). >> >> Which UHD version are you using? >> >> I suggest opening an issue on https://github.com/EttusResearch/uhd/issues. >> If you can, share your code for configuring the SPI rate and the the >> oscilloscope screen shot. >> >> Thanks, >> >> Wade >> >> On Thu, Jun 26, 2025 at 8:25 PM Rob Kossler <[email protected]> wrote: >> >>> Hi Wade, >>> Thanks for the response. Here are the answers: >>> - here is the URL >>> <https://files.ettus.com/manual/page_x400_gpio_api.html#x4x0_spi_r_w> >>> for the equation in the UHD manual >>> - I am using the X410 with UC_200 FPGA image with master clock rate of >>> 245.76 MHz >>> - The function usrp->get_radio_control()->get_rate() returns 245.76 MHz >>> - The SPI clock as seen on my oscilloscope is half the rate I expect >>> from the equation if I use 245.76 MHz >>> - I wasn't sure if the factor of 2 was because of the half-cycle issue >>> you mentioned or if it had something to do with the radio clock perhaps >>> running at 122.88 MHz with 2 samples per cycle. >>> >>> Rob >>> >>> On Thu, Jun 26, 2025 at 4:37 PM Wade Fife <[email protected]> wrote: >>> >>>> Actually it looks like X410 and X440 use different clocks for the SPI >>>> core. Can you confirm which device you saw this on and what master clock >>>> rate you're using? >>>> >>>> For X410 with 200 MHz bandwidth, for example, I think the "Radio_Clk" >>>> value you should use in that original equation in the documentation is >>>> 245.76 MHz or 250 MHz, depending on your master clock rate. So: >>>> >>>> SPI_clk = 245.76 MHz / (divider + 1) >>>> >>>> What value was returned by usrp->get_radio_control()->get_rate()? >>>> >>>> Wade >>>> >>>> >>>> On Thu, Jun 26, 2025 at 2:41 PM Wade Fife <[email protected]> wrote: >>>> >>>>> Hi Rob, >>>>> >>>>> I believe the underlying code that implements this is here: >>>>> >>>>> >>>>> https://github.com/EttusResearch/uhd/blob/c354764c93b49c90be08958f942b9bcb7704cbd5/fpga/usrp3/lib/control/simple_spi_core.v#L182 >>>>> >>>>> It looks like the clock is inverted every divider+1 cycles, meaning >>>>> divider+1 is half the SPI clock period, not the full period. If so, the >>>>> frequency of the SPI clock would actually be (Radio_Clk / (divider + 1)) / >>>>> 2. >>>>> >>>>> That seems to agree with what you're seeing? Just to confirm, can you >>>>> share the URL for the documentation with this equation? >>>>> >>>>> Wade >>>>> >>>>> >>>>> >>>>> On Wed, Jun 25, 2025 at 4:25 PM Rob Kossler via USRP-users < >>>>> [email protected]> wrote: >>>>> >>>>>> Hi, >>>>>> The equation in the UHD manual for the X410 SPI clock rate is: >>>>>> SPI_clk = Radio_clk / (divider + 1) >>>>>> However, I'm seeing half of that rate if I use the function: >>>>>> Radio_clk = usrp->get_radio_control()->get_rate(); >>>>>> Note that this returns the sample rate. I'm wondering if maybe the >>>>>> radio clock rate is half of the sample rate because it processes multiple >>>>>> samples per clock cycle. >>>>>> >>>>>> So, basically, my question is: what function or functions should I >>>>>> call to determine the Radio clock rate needed for the equation above? Or >>>>>> is >>>>>> the equation wrong? >>>>>> >>>>>> Thanks. >>>>>> Rob >>>>>> >>>>>> _______________________________________________ >>>>>> USRP-users mailing list -- [email protected] >>>>>> To unsubscribe send an email to [email protected] >>>>>> >>>>>
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