Francesco Romani has uploaded a new change for review. Change subject: sampling: refactor tests ......................................................................
sampling: refactor tests Refactor the tests to make them clearer and to make room for further improvements. Change-Id: Ic88fc4e5f625ed97aa68bba87e1979ff06621b5b Backport-To: 4.0 Backport-To: 3.6 Bug-Url: https://bugzilla.redhat.com/1357798 Signed-off-by: Francesco Romani <from...@redhat.com> --- M tests/samplingTests.py 1 file changed, 33 insertions(+), 13 deletions(-) git pull ssh://gerrit.ovirt.org:29418/vdsm refs/changes/09/61309/1 diff --git a/tests/samplingTests.py b/tests/samplingTests.py index caca2c6..bba216f 100644 --- a/tests/samplingTests.py +++ b/tests/samplingTests.py @@ -229,17 +229,37 @@ self.assertEqual(memorySample.nodesMemSample, expected) +class FakeClock(object): + + STEP = 1 + + def __init__(self, value=0): + self.value = value + self._frozen = False + + @property + def frozen(self): + return self._frozen + + def freeze(self, value=None): + if value is not None: + self.value = value + self._frozen = True + + def unfreeze(self): + self._frozen = False + + def __call__(self): + if not self._frozen: + self.value += self.STEP + return self.value + + class StatsCacheTests(TestCaseBase): - FAKE_CLOCK_STEP = 1 - def setUp(self): - self.clock = 0 + self.fake_monotonic_time = FakeClock() self.cache = sampling.StatsCache(clock=self.fake_monotonic_time) - - def fake_monotonic_time(self): - self.clock += self.FAKE_CLOCK_STEP - return self.clock def test_empty(self): res = self.cache.get('x') # vmid not relevant @@ -261,8 +281,8 @@ self.assertEqual(res, ('foo', 'bar', - self.FAKE_CLOCK_STEP, - self.FAKE_CLOCK_STEP)) + FakeClock.STEP, + FakeClock.STEP)) def test_get_missing(self): self._feed_cache(( @@ -282,8 +302,8 @@ self.assertEqual(res, ('bar', 'baz', - self.FAKE_CLOCK_STEP, - self.FAKE_CLOCK_STEP)) + FakeClock.STEP, + FakeClock.STEP)) def test_put_out_of_order(self): self._feed_cache(( @@ -295,7 +315,7 @@ self.assertEqual(res, ('foo', 'baz', - self.FAKE_CLOCK_STEP, + FakeClock.STEP, 0)) def test_skip_one_cycle(self): @@ -308,7 +328,7 @@ ({'a': 'baz', 'b': 'baz'}, 3), )) self.assertEqual(self.cache.get('a'), - ('bar', 'baz', 1, self.FAKE_CLOCK_STEP)) + ('bar', 'baz', 1, FakeClock.STEP)) self.assertEqual(self.cache.get('b'), sampling.EMPTY_SAMPLE) -- To view, visit https://gerrit.ovirt.org/61309 To unsubscribe, visit https://gerrit.ovirt.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic88fc4e5f625ed97aa68bba87e1979ff06621b5b Gerrit-PatchSet: 1 Gerrit-Project: vdsm Gerrit-Branch: master Gerrit-Owner: Francesco Romani <from...@redhat.com> _______________________________________________ vdsm-patches mailing list vdsm-patches@lists.fedorahosted.org https://lists.fedorahosted.org/admin/lists/vdsm-patches@lists.fedorahosted.org
