Hi,
In VHDL I many times need to change the following code:
component AAA
port (
i1 : in std_ulogic;
i2 : in std_ulogic;
o1 : out std_ulogic;
o2 : out std_ulogic);
end component AAA;
into:
inst_AAA : AAA
port map (
i1 => in ,
i1 => in ,
o1 => out,
o2 => out,
o2 => out);
where:
- AAA is the variable name, so it can be anything:
- The number of in and outputs (here 2 inputs i1 and i2, and 2 outputs o1
and o2) can be both from 1 till anything)
How to do this S&R
Rgds,
Eric
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