> In VHDL I many times need to change the following code:
>
> component AAA
> port (
> i1 : in std_ulogic;
> i2 : in std_ulogic;
> o1 : out std_ulogic;
> o2 : out std_ulogic);
> end component AAA;
>
> into:
>
> inst_AAA : AAA
> port map (
> i1 => in ,
> i1 => in ,
> o1 => out,
> o2 => out,
> o2 => out);
>
> where:
> - AAA is the variable name, so it can be anything:
> - The number of in and outputs (here 2 inputs i1 and i2, and 2 outputs o1
> and o2) can be both from 1 till anything)
You may have to clarify. I'm not sure how this mapping is taking
place. It looks like you start with two inputs ("i1" and "i2")
and two outputs ("o1", and "o2") and you want to map them to two
inputs ("i1" and "i1" again) and *three* outputs ("o1", "o2", and
"o2" again).
So questions would include:
-what governs when i2 becomes i1?
-what governs when/why o2 gets doubled?
Otherwise, it looks like you may want something like
:'<,'>s/std_ulogic;/,
:*s/:/=>
where you create the range by getting inside the parens and using
"vi(" to highlight the lines for those parens. (In that 2nd one,
the asterisk is a short-hand notation for the "'<,'>", an
little-known or oft-overlooked feature of vim that I use fairly
regularly)
HTH,
-tim
PS: This is fun...I'm learning little bits of VHDL merely by
hanging out on a mailing list for a *text-editor* :) Looks like
fun stuff.
