[deleted]
You may have to clarify. I'm not sure how this mapping is taking
place. It looks like you start with two inputs ("i1" and "i2")
and two outputs ("o1", and "o2") and you want to map them to two
inputs ("i1" and "i1" again) and *three* outputs ("o1", "o2", and
"o2" again).
My stupidity
I've made two typo's:
It must be
component AAA
port (
i1 : in std_ulogic;
i2 : in std_ulogic;
o1 : out std_ulogic;
o2 : out std_ulogic);
end component AAA;
to become:
inst_AAA : AAA
port map (
i1 => in ,
i2 => in ,
o1 => out,
o2 => out);
So questions would include:
-what governs when i2 becomes i1?
For S&R simplyfing I've left the two in , and the two out as
text-placeholders
When the S&R is done I need to manual change these.
For example, it would become
i1 => A ,
i2 => B ,
o1 => C,
o2 => D);
-what governs when/why o2 gets doubled?
This is my typo. It should have only one o2.
Otherwise, it looks like you may want something like
:'<,'>s/std_ulogic;/,
:*s/:/=>
where you create the range by getting inside the parens and using
"vi(" to highlight the lines for those parens. (In that 2nd one,
the asterisk is a short-hand notation for the "'<,'>", an
little-known or oft-overlooked feature of vim that I use fairly
regularly)
[deleted]
PS: This is fun...I'm learning little bits of VHDL merely by
hanging out on a mailing list for a *text-editor* :) Looks like
fun stuff.
Yes VHDL is fun.
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