On 21.09.2020 15:27, Julien Grall wrote: > I think this part is racy at least on non-x86 platform as x86 seems to > implement smp_mb() with a strong memory barrier (mfence).
The "strength" of the memory barrier doesn't matter here imo. It's the fully coherent memory model (for WB type memory) which makes this be fine on x86. The barrier still only guarantees ordering, not visibility. Jan
