On 21.09.2020 15:35, Durrant, Paul wrote: >> From: Jan Beulich <jbeul...@suse.com> >> Sent: 21 September 2020 14:32 >> >> On 21.09.2020 15:27, Julien Grall wrote: >>> I think this part is racy at least on non-x86 platform as x86 seems to >>> implement smp_mb() with a strong memory barrier (mfence). >> >> The "strength" of the memory barrier doesn't matter here imo. It's >> the fully coherent memory model (for WB type memory) which makes >> this be fine on x86. The barrier still only guarantees ordering, >> not visibility. >> > > In which case I misunderstood what the 'smp' means in this context then.
I find this confusing too, at times. But according to my reading of the doc the "smp" in there really only means "simple compiler barrier when UP". Jan
