> -----Original Message----- > From: Jan Beulich <jbeul...@suse.com> > Sent: 21 September 2020 14:32 > To: Julien Grall <jul...@xen.org> > Cc: Durrant, Paul <pdurr...@amazon.co.uk>; Stefano Stabellini > <sstabell...@kernel.org>; > andrew.coop...@citrix.com; George Dunlap <george.dun...@citrix.com>; Xia, > Hongyan > <hongy...@amazon.com>; xen-devel@lists.xenproject.org > Subject: RE: [EXTERNAL] Memory ordering question in the shutdown deferral code > > CAUTION: This email originated from outside of the organization. Do not click > links or open > attachments unless you can confirm the sender and know the content is safe. > > > > On 21.09.2020 15:27, Julien Grall wrote: > > I think this part is racy at least on non-x86 platform as x86 seems to > > implement smp_mb() with a strong memory barrier (mfence). > > The "strength" of the memory barrier doesn't matter here imo. It's > the fully coherent memory model (for WB type memory) which makes > this be fine on x86. The barrier still only guarantees ordering, > not visibility. >
In which case I misunderstood what the 'smp' means in this context then. Paul
