Need to initialize the submodules after switching or checking out to the target branch.
Run make init will initialize the submodules correctly (same as git submodule update --init). Then it should be compiled as expected.
---- Replied Message ----
| From | Tariq Kurd<tariq.k...@codasip.com> |
| Date | 01/10/2024 20:19 |
| To | Yinan Xu<xuyi...@ict.ac.cn> |
| Cc | xiangshan-all@ict.ac.cn<xiangshan-all@ict.ac.cn> |
| Subject | Re: Getting started with NanHu |
Hi Yinnan Xu,
Thank you.
I have tried to build nanhu but I think I am having two problems.
I did this:
export NOOP_HOME=$PWD/XiangShan
export NEMU_HOME=$PWD/NEMU
export AM_HOME=$PWD/nexus-am
#needed to get mill on the path
PATH=$PATH:$NOOP_HOME
cd $NOOP_HOME
git switch nanhu
make
This is my script.
If I run on the master branch (git switch master) then I get some warnings and an error
[warn] fudian/src/main/scala/fudian/FDIV.scala:625:24: Dynamic index with width 33 is too large for extractee of width 26
[warn] aHeadReg := Mux(aIter(j << 1),
[warn] ^
[warn] There were 1 warning(s) during hardware elaboration.
[warn] fudian/src/main/scala/fudian/FDIV.scala:625:24: Dynamic index with width 33 is too large for extractee of width 55
[warn] aHeadReg := Mux(aIter(j << 1),
[warn] ^
[warn] There were 1 warning(s) during hardware elaboration.
[warn] aHeadReg := Mux(aIter(j << 1),
[warn] ^
[warn] There were 1 warning(s) during hardware elaboration.
[warn] fudian/src/main/scala/fudian/FDIV.scala:625:24: Dynamic index with width 33 is too large for extractee of width 55
[warn] aHeadReg := Mux(aIter(j << 1),
[warn] ^
[warn] There were 1 warning(s) during hardware elaboration.
[warn] rocket-chip/src/main/scala/devices/debug/Debug.scala:1727:37: Dynamic index with width 2 is too large for extractee of width 1
[warn] val hartHalted = haltedBitRegs(selectedHartReg)
[warn] ^
[warn] val hartHalted = haltedBitRegs(selectedHartReg)
[warn] ^
1 targets failed
xiangshan[chisel3].runMain subprocess failed
make: *** [Makefile:121: build/XSTop.v] Error 1
xiangshan[chisel3].runMain subprocess failed
make: *** [Makefile:121: build/XSTop.v] Error 1
If I run on the nanhu branch (git switch nanhu) then the environment is broken
[tariq.kurd@NB128 XiangShan]$ make
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build \
--config DefaultConfig --full-stacktrace --output-file XSTop.v \
--infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
--gen-mem-verilog full --num-cores 1 \
--disable-all --remove-assert --fpga-platform
Cannot resolve $file import: /home/tariq.kurd/gitlab/a90x/XiangShan/XiangShan_NanHu/XiangShan/rocket-chip/api-config-chipsalliance/build-rules/mill/build.sc
make: *** [Makefile:73: build/XSTop.v] Error 1
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build \
--config DefaultConfig --full-stacktrace --output-file XSTop.v \
--infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
--gen-mem-verilog full --num-cores 1 \
--disable-all --remove-assert --fpga-platform
Cannot resolve $file import: /home/tariq.kurd/gitlab/a90x/XiangShan/XiangShan_NanHu/XiangShan/rocket-chip/api-config-chipsalliance/build-rules/mill/build.sc
make: *** [Makefile:73: build/XSTop.v] Error 1
Can you help? Is it related to the mill installation maybe?
谢谢你帮我一个忙
Tariq
On Wed, 10 Jan 2024 at 10:41, Yinan Xu <xuyi...@ict.ac.cn> wrote:
Hi,Thank you for your interests in XiangShan. You can try the nanhu branch for NANHU v1 and southlake branch for NANHU v2 (with DFT support but smaller caches).Nanhu-v2 branch is not used any more. We will clean it up to avoid confusions.Best,Yinan Xu---- Replied Message ----
From Tariq Kurd<tariq.k...@codasip.com> Date 01/10/2024 18:33 To xiangshan-all@ict.ac.cn<xiangshan-all@ict.ac.cn> Subject Getting started with NanHu Hi,I'd like to try out the NanHu core.Should I check out this branch: https://github.com/OpenXiangShan/XiangShan/tree/nanhuor what about https://github.com/OpenXiangShan/XiangShan/tree/nanhu-v2?what's the best place to start from, I'd like to analyse the designThanksTariq Kurd--
