Re: Getting started with NanHu

Wed, 10 Jan 2024 17:33:58 -0800

Hi Tariq,


sbt is not used nor needed for XiangShan. We are using mill as the scala build tool.

The only few tools required for building the verilog for XianghShan is mill (version specified in .mill-version and automatically detected/downloaded by the mill in PATH), JDK (>=11, <=17). I think no other tools are required.

To make it clear, what we need is a git repo with the correct submodules as specified by git. Every time switching to a new branch, make sure the local directory has up-to-date submodules (by checking git status).

After `make verilog` or other commands, the verilog will be generated at `build/SimTop.v` as well as the fir file `build/SimTop.fir`. The fir file is hundreds of MBs. I just double-checked it should be there.

Feel free to let me know for further issues. GitHub issues are welcomed and preferred for detailed discussions.


Best,
Yinan

---- Replied Message ----
I followed the instructions in https://github.com/OpenXiangShan/xs-env and I got further.
I don't get the XSTop.fir file - where in the installation instructions is how to install sbt?
It doesn't seem to be listed, and so I don't have it. Maybe that's the problem.

Tariq

On Wed, 10 Jan 2024 at 15:37, Tariq Kurd <tariq.k...@codasip.com> wrote:
thanks - I got much further but I still have a problem

[tariq.kurd@NB128 XiangShan]$ make init && make
git submodule update --init
cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build                      \
        --config DefaultConfig --full-stacktrace --output-file XSTop.v    \
        --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
        --gen-mem-verilog full --num-cores 1             \
        --disable-all --remove-assert --fpga-platform
[build.sc] [49/53] compile
[info] compiling 4 Scala sources to /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/out/mill-build/compile.dest/classes ...
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/build.sc:148:23: not found: type Tests
[error]   object test extends Tests with TestModule.ScalaTest {
[error]                       ^
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/rocket-chip/common.sc:96:37: value repositories is not a member of mill.define.Module.BaseClass with mill.scalalib.SbtModule with mill.scalalib.PublishModule
[error]   override def repositories = super.repositories ++ Seq(
[error]                                     ^
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/rocket-chip/common.sc:50:23: not found: type Tests
[error]   object test extends Tests {
[error]                       ^
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/rocket-chip/hardfloat/build.sc:47:30: value repositories is not a member of mill.define.Module.BaseClass with mill.scalalib.ScalaModule with mill.scalalib.SbtModule with mill.scalalib.PublishModule
[error]   def repositories() = super.repositories ++ Seq(
[error]                              ^
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/rocket-chip/hardfloat/build.sc:52:23: not found: type Tests
[error]   object test extends Tests {
[error]                       ^
[warn] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/out/mill-build/generateScriptSources.dest/millbuild/rocket-chip/api-config-chipsalliance/build-rules/mill/build.sc:31:49: symbol literal is deprecated; use Symbol("design") instead [quickfixable]
[warn]   def millSourcePath = os.pwd / os.up / os.up / 'design / 'craft
[warn]                                                 ^
[warn] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/out/mill-build/generateScriptSources.dest/millbuild/rocket-chip/api-config-chipsalliance/build-rules/mill/build.sc:31:59: symbol literal is deprecated; use Symbol("craft") instead [quickfixable]
[warn]   def millSourcePath = os.pwd / os.up / os.up / 'design / 'craft
[warn]                                                           ^
[error] /home/tariq.kurd/github/xiangshan/nanhu/XiangShan/rocket-chip/common.sc:57:28: T{} members must be defs defined in a Cacher class/trait/object body
[error]     def testFrameworks = T {
[error]                            ^
[warn] two warnings found
[error] 6 errors found
1 targets failed
compile Compilation failed
make: *** [Makefile:73: build/XSTop.v] Error 1

can you help?

Thanks

Tariq



On Wed, 10 Jan 2024 at 12:33, Yinan Xu <xuyi...@ict.ac.cn> wrote:
Need to initialize the submodules after switching or checking out to the target branch.

Run make init will initialize the submodules correctly (same as git submodule update --init). Then it should be compiled as expected. 
---- Replied Message ----
Hi Yinnan Xu,

Thank you.
I have tried to build nanhu but I think I am having two problems.
I did this:

git clone https://github.com/OpenXiangShan/XiangShan.git --recurse-submodules
git clone https://github.com/OpenXiangShan/NEMU.git --recurse-submodules
git clone https://github.com/OpenXiangShan/nexus-am.git --recurse-submodules

export NOOP_HOME=$PWD/XiangShan
export NEMU_HOME=$PWD/NEMU
export AM_HOME=$PWD/nexus-am

#needed to get mill on the path
PATH=$PATH:$NOOP_HOME

cd $NOOP_HOME
git switch nanhu


make


This is my script.
If I run on the master branch (git switch master) then I get some warnings and an error

[warn] fudian/src/main/scala/fudian/FDIV.scala:625:24: Dynamic index with width 33 is too large for extractee of width 26
[warn]   aHeadReg := Mux(aIter(j << 1),
[warn]                        ^
[warn] There were 1 warning(s) during hardware elaboration.
[warn] fudian/src/main/scala/fudian/FDIV.scala:625:24: Dynamic index with width 33 is too large for extractee of width 55
[warn]   aHeadReg := Mux(aIter(j << 1),
[warn]                        ^
[warn] There were 1 warning(s) during hardware elaboration.

[warn] rocket-chip/src/main/scala/devices/debug/Debug.scala:1727:37: Dynamic index with width 2 is too large for extractee of width 1
[warn]     val hartHalted   = haltedBitRegs(selectedHartReg)
[warn]                                     ^
1 targets failed
xiangshan[chisel3].runMain subprocess failed
make: *** [Makefile:121: build/XSTop.v] Error 1


If I run on the nanhu branch (git switch nanhu) then the environment is broken

[tariq.kurd@NB128 XiangShan]$ make
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build                      \
        --config DefaultConfig --full-stacktrace --output-file XSTop.v    \
        --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
        --gen-mem-verilog full --num-cores 1             \
        --disable-all --remove-assert --fpga-platform
Cannot resolve $file import: /home/tariq.kurd/gitlab/a90x/XiangShan/XiangShan_NanHu/XiangShan/rocket-chip/api-config-chipsalliance/build-rules/mill/build.sc
make: *** [Makefile:73: build/XSTop.v] Error 1

Can you help? Is it related to the mill installation maybe?

谢谢你帮我一个忙

Tariq


On Wed, 10 Jan 2024 at 10:41, Yinan Xu <xuyi...@ict.ac.cn> wrote:
Hi,

Thank you for your interests in XiangShan. You can try the nanhu branch for NANHU v1 and southlake branch for NANHU v2 (with DFT support but smaller caches).

Nanhu-v2 branch is not used any more. We will clean it up to avoid confusions. 

Best,
Yinan Xu
---- Replied Message ----
FromTariq Kurd<tariq.k...@codasip.com>
Date01/10/2024 18:33
Toxiangshan-all@ict.ac.cn<xiangshan-all@ict.ac.cn>
SubjectGetting started with NanHu
Hi,

I'd like to try out the NanHu core.
Should I check out this branch: https://github.com/OpenXiangShan/XiangShan/tree/nanhu
?

what's the best place to start from, I'd like to analyse the design

Thanks

Tariq Kurd

--
Tariq Kurd
Lead IP Architect
Codasip Design Center Bristol, United Kingdom
→ www.codasip.com

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