Thanks Dan! Much appreciated!
From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Thursday, April 25, 2019 9:51 AM
To: CASPER Mailing List
Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx transceivers
hi dave,
i don't know about using the SERDES as ADC's.
paul horowitz
Hi Jack,
>> I did have the unfair advantage of sharing a lab with him :)
As did I - he visited OVRO for a while - but as you comment ... 2010 is a
million years ago :)
Many thanks for the name, and the links to additional materials. Myron (GPS
person) subscribes to the CASPER list, so he now
I did have the unfair advantage of sharing a lab with him :)
On Thu, 25 Apr 2019 at 18:56, 'Hawkins, David W (334B)' via
casper@lists.berkeley.edu wrote:
>
> Jack - you rock - Adam was the name I was recalling, but I could not think of
> his last name. Thanks!
>
> -Original Message-
>
Jack - you rock - Adam was the name I was recalling, but I could not think of
his last name. Thanks!
-Original Message-
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: Thursday, April 25, 2019 9:55 AM
To: casper
Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx
Hi Dave,
A million years ago (circa 2010) Adam Coates (then grad student of
Prof Mike Jones at Oxford --
https://www2.physics.ox.ac.uk/contacts/people/jonesmi) was looking at
this using ROACH1 (virtex5) transceivers to sample at ~3GHz. IIRC Adam
went into industry after his PhD, and I'm not sure
hi dave,
i don't know about using the SERDES as ADC's.
paul horowitz and andrew howard used the xilinx LVDS inputs as flash ADC
comparators
sampling at about 1 Gsps, they built thousands of multilevel ADC's,
biasing one input of each comparator at different DC levels using a
resistor divider
Hi All,
Has anyone on the CASPER list investigated using the Xilinx transceivers as
1-bit ADCs?
Transceiver receivers can be kept coherent to a reference clock by configuring
the receiver clock-and-data-recovery unit not to recover the clock from the
incoming data stream.
There are some
Hi Nikita,
Can you post a link to your model please -- i suspect there's
something funny with you one of the simulation inputs is configured.
Cheers
Jack
On Thu, 25 Apr 2019 at 16:33, 'Nikita Rathore' via
casper@lists.berkeley.edu wrote:
>
> I am working on simulink design of 2 element
I am working on simulink design of 2 element interferometer but I am having
following issue in simulation.
- Version Log
--
Version Path
System Generator /opt/Xilinx/14.7/ISE_DS/ISE/sysgen
Hi Indrajit
This should do something like what you want to do I think.
Cheers
Andrew
On Thu, Apr 25, 2019 at 6:53 AM Indrajit Barve wrote:
> Hello all,
>
> I would like to implement a FIFO with input port data type depth and
> width of 2048 X 32 and output port data type 1024 X 64.
Hi Indrajit,
I'm surprised that the Xilinx FIFO block doesn't give the option of
having ports of two different widths. However, if it doesn't, the
easiest thing to do might be to use a dual port RAM, which does allow
the two interfaces to have different widths. If you can explain a bit
more about
Is the fpg file empty, if not do a less on the file - the first couple
of lines should be human readable register definitions, followed by
the bitstream to check that it looks reasonble. Also see if you can
ping the IP of the roach board, and see if telnet to its port 7147
works
regards
marc
On
I am using MATLAB R2012b, Xilinx 14.7 and Roach2 board. Yes, I have .fpg
file and I am trying to burn fpga with the generated .fpg file using
casperfpga but in that case I am getting following issue:
import casperfpga
> >>> fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.100.192')
> >>>
Not sure what hardware you are working on, but your system might have
generated a newer .fpg file ? If this isn't the case, maybe the mkbof
executable isn't built for your build machine architecture (x86 vs
amd64) or c/linker revision ? See if you can run the mkbof executable
manually ?
regards
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