http://bugzilla.kernel.org/show_bug.cgi?id=11541





------- Comment #85 from [email protected]  2009-03-05 02:27 -------
Thanks for that debug data.

This shows that, the mainline kernel w/o my patch (attachment #20412)
is (potentially(*)) changing RdMem/WrMem bits on CPUs 1 and 2 from:

[    0.010000] MTRRfixed(268): 0x1818181818181818
[    0.010000] MTRRfixed(269): 0x1818181818181818
...
[    0.010000] MTRRfixed(26e): 0x1818181818181818
[    0.010000] MTRRfixed(26f): 0x1818181818181818

(i.e. reads and writes to the specified ranges are going to DRAM)
to (see first output for CPU 0):

[    0.000000] MTRRfixed(268): 0x1010101010101010
[    0.000000] MTRRfixed(269): 0x1010101010101010
...
[    0.000000] MTRRfixed(26e): 0x1515151515151515
[    0.000000] MTRRfixed(26f): 0x1515151515151515

This in turn means that reads got to DRAM but writes go to IO.
We just do not know what the BIOS has performed on CPU0 with
those RdMem/WrMem settings, maybe it is changing that later on.
But as we don't know it we shouldn't touch those bits.

(*) "potentially" because my debug patch did not show RdMem/WrMem bits
when fixed MTRR were set on CPU2 and CPU3.

Furthermore the mainline kernel w/ and w/o my patch
did change the memory type for following ranches on
CPUs 2 and 3:

[    0.010000] MTRRfixed(26e): 0x1818181818181818
[    0.010000] MTRRfixed(26f): 0x1818181818181818

which was type 0 (uncached) (when masking the RdMem/WrMem bits)
to

[    0.130000] MTRRfixed(26e): 0x0505050505050505
[    0.130000] MTRRfixed(26f): 0x0505050505050505

i.e. type 5 (write-protect).

If there are no objections I'll submit
"[PATCH] x86: mtrr: don't modify RdDram/WrDram bits of fixed MTRRs"
for upstream integration.


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