> On 01/06/2015 03:26 PM, Sébastien Bourdeauducq wrote: > > Or sample SYNC_CLK with a discrete flip-flop or latch near each DDS > > chip and trigger them with a skew-matched on-board clocking network > > pulsed by the FPGA through a scanned ODELAY. Then low-performance > > multiplexers, shared buses and skew are acceptable at the flip-flop > outputs. > > http://www.onsemi.com/pub/Collateral/NB4L52-D.PDF has 150ps of setup + > hold time, so the part-to-part variation in input characteristics should not > be > significant. And it takes LVCMOS and even contains a comparator.
This would work, but then one has the task of distributing a skew-matched on-board clock in addition to the SYNC_IN which is already being distributed. There is the advantage that this would make the SYNC_CLKs aligned at the DDS chips automatically (to within the skew matching of the clocking network). Something like http://www.ti.com/product/cdclvp1216 would provide a suitable clock distribution solution. For the readback, one multiplexer is here (http://www.idt.com/products/clocks-timing/clock-distribution-ics/fanout-buffers-clock-dividers-and-multiplexers/853s012i-121-differential-33v25v-lvpecl-clockdata-multiplexer), although there would need to be an LVPECL-to-LVCMOS translator stage afterwards as well. So now the system would have the following components on the FMC backplane and DDS cards: * SYNC_IN 1:12 clock distribution with lines to each DDS, driven by FPGA with variable ODELAY * SYNC_CLK LVCMOS-to-LVPECL latch on each DDS card * SYNC_CLK latch clock 1:12 distribution, with matched skew lines to each DDS, driven by FPGA with variable ODELAY * SYNC_CLK 12:1 multiplexer with LVPECL-to-LVCMOS translation to FPGA input (these do no need to be fast because of the fast latch on the DDS cards) It might be a challenge to get all this on the circuit board! _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
