> > This is part of why I have been proposing LVCMOS signals instead of > > trying for crazy bandwidths with differential signaling - > > I don't see how LVCMOS helps with signal integrity over pin headers given > that the bandwidth depends on the requirement on the rise time of the > signal (and not really on the signalling standard).
LVCMOS does not help with signal integrity; what I had meant to express with my statement is that if you are just using LVCMOS (and its correspondingly slow-ish rise times relative to fast differential standards like LVPECL/LVDS) then the question of the connector to the DDS cards is not as crucial, and you can perhaps get away with the existing 2mm pin header. > > the current design calls for the use of 2mm pin headers, back compatible > with the existing DDS boards, which are not going to give us the best > performance. > > > > If we are OK with losing the back-compatibility with previous designs, we > can think about using high-speed connectors e.g. SAMTEC QRM8, which are > designed for this sort of thing. > > If plain pin headers can not do the required < 300 ps edges (for the > AD9915 SYNC_IN/OUT scheme or for reliable SYNC_CLK detection) the > question has a simple answer. And if new bus connectors are required, this is > the time to choose a COTS rack/bus system and not invent another. So are you suggesting we should move to something like XMC or MicroTCA for the DDS cards? We should perhaps have a group discussion about these various topics. I know that Joe has also been pushing to put our hardware in some sort of nice commercial rack-able format too. Originally the motivation for using this FMC backplane/DDS riser scheme was that it required minimal modification of an existing design. Now that we are trying to do the DDS synchronization using the FPGA and traces on the backplane as well, it's getting a bit more involved. However, I don't think the level of complexity approaches what might be necessary if we move to a COTS crate architecture like MicroTCA for the DDS's, where it would probably be necessary to have a distributed RTIO core and an FPGA on each card to handle communications, which run over gigabit Ethernet or PCIe in those standards. For my money, this would be an entirely new project at yet another level of complexity. It's great for scaling up, and I agree it is better if one is thinking in a truly "big picture" way, but the up-front cost is substantial and I think the value for our 5-year experimental horizon relative to a one-off solution like changing connectors on the existing FMC backplane design is not par ticularly high. Given the level of complexity for re-routing the board at this point, and the amount of time it would take for me to do all the work, I have been thinking I would send the backplane (and potentially the DDS cards as well) out to an external PCB design/layout guy to do the grunt work. This would also make it go faster, I think, once we have settled on a design we like. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
