On Tue, Jan 6, 2015 at 12:14 PM, Slichter, Daniel H. <daniel.slich...@nist.gov> wrote: > So now the system would have the following components on the FMC backplane > and DDS cards: > > * SYNC_IN 1:12 clock distribution with lines to each DDS, driven by FPGA with > variable ODELAY > * SYNC_CLK LVCMOS-to-LVPECL latch on each DDS card > * SYNC_CLK latch clock 1:12 distribution, with matched skew lines to each > DDS, driven by FPGA with variable ODELAY > * SYNC_CLK 12:1 multiplexer with LVPECL-to-LVCMOS translation to FPGA input > (these do no need to be fast because of the fast latch on the DDS cards)
What connector do you want to use to get these fast-edge signals from the backplane to the dds cards and back? -- Robert Jordens. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
