well, there are verified OH designs of such cards: 32 channel TTL IO http://www.ohwr.org/projects/fmc-dio-32chttla/wiki slow DAC card with some IOs and slow ADCs. http://www.ohwr.org/projects/fmc-dac100m14b16cha-adc2m14b4cha/wiki
On 31 March 2016 at 01:45, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > One further question: is there a plan to make a “TTL” card or a > multichannel “slow” DAC card (e.g. for trap voltages), using a Centronics > or d-sub type connector? These could both be more readily accomplished > with their own FMC modules if we go with this architecture. > > > > *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com] > *Sent:* Wednesday, March 30, 2016 3:36 PM > > *To:* Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> > *Cc:* Robert Jördens <r...@m-labs.hk>; Grzegorz Kasprowicz < > gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) < > david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>; > artiq@lists.m-labs.hk > *Subject:* Re: [ARTIQ] FW: initial specification of the project > > > > Here is example of CERN carrier with analogue voltages: > http://www.ohwr.org/projects/fmc-pci-carrier/wiki > "+5V, -2V, -5V2 and -12V optionally wired on HPC pins" > > look here > https://edms.cern.ch/ui/file/1098639/1/EDA-02118-V1-1_sch.pdf > > page 3 > > > > On 30 March 2016 at 23:17, Slichter, Daniel H. (Fed) < > daniel.slich...@nist.gov> wrote: > > We definitely need +/- 15V for the low frequency (e.g. trap electrode) > amplifiers. Many low noise amplifiers and RF components run off +5V or +/- > 5V and have substantial current draws, so if you pull everything from +/- > 15V rails you are tripling your power dissipation and you end up with very > hot regulators. The DACs and ADCs will be dissipating a fair amount of > power already so we want to try to keep the power budget under control. > Other than that, I don’t see major reasons why one couldn’t run fewer > analog rails. I think we are better off with DC/DC converters on the AMC > card making a number of rails, which then have some filtering/regulation on > the AMC card and then a final stage of LDO regulation on the FMC > daughtercard itself, as close to the amplifiers etc as possible. > > > > Using the alternating grounds a la CERN seems like a suitable solution to > me for sending in these additional analog rails. > > > > *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com] > *Sent:* Wednesday, March 30, 2016 3:13 PM > *To:* Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> > *Cc:* Robert Jördens <r...@m-labs.hk>; Grzegorz Kasprowicz < > gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) < > david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>; > artiq@lists.m-labs.hk > *Subject:* Re: [ARTIQ] FW: initial specification of the project > > > > Well, CERN does it in their FMC carriers. They use HPC routed like LPC and > then some of grounds are used as symmetrical analog supplies. In this way > if you plug wrong board, it will short the supply but no damage will occur. > > I assume that low nosie DC/DC converters + LDOs will be installed on the > AMC board. > > Do we need all these voltages, especially +/-5 and +/- 15? Won't single > +/- 8 or +/- 15V be sufficient? > > Greg > > > > On 30 March 2016 at 23:08, Slichter, Daniel H. (Fed) < > daniel.slich...@nist.gov> wrote: > > > > Actually HPC with LPC IO assignment and 8 x GTP links is popular > configuration > > So you have 34 LVDS pairs and 8 GTP links. > > > > If this works for you then I don’t have major objections. The other issue > to consider is power rails, since for the analog circuitry we will probably > want +/- 5V, +/- 15V as well as +3.3V, +1.8V, +12V. Can we put these > through on the FMC without breaking back compatibility? For example, one > rail on each of the 4 VADJ pins? I am sure this would not be VITA 57 > compliant….and we don’t want switching converters on the FMC daughtercard > for space and noise reasons both. > > > > >
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