Just to clarify this: We do need a pretty large FPGA (7K325T) on the AMC cards due to the resource requirements of signal processing. Then we have 16 GTX 12.5Gbps transceivers, but if we want to make the two FMCs identical and capable of receiving fast 4-channel DACs with 8 lanes, then we have no more transceivers. So the IOSERDES option is still interesting.
Greg - How many data lanes can we easily have between the MCH and each AMC with a star topology backplane? Sébastien On Wednesday, 30 March 2016 9:33:51 PM HKT Grzegorz Kasprowicz wrote: > Hi all > I like that idea - in this way we can do it really affordable with lower end > FPGAs and still compatible with MTCA. > If we place all RF stuff on the modules, with RF connectors mounted directly > on the front panel, this could work. > How we would deliver the clocks? Using external SMA connectors? > The only think I worry about is performance of the DACs. > ZynQ US+ can run IOserdes with almost 2Gbit/s performance - one can make > 1000base-x directly on IO pins using oversampling technique. > Greg > > -----Original Message----- > From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] > Sent: Wednesday, March 30, 2016 1:50 PM > To: Grzegorz Kasprowicz <kaspr...@gmail.com> > Cc: 'Slichter, Daniel H. (Fed)' <daniel.slich...@nist.gov>; 'Grzegorz > Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] FW: initial specification of the project > > On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote: > > - they can be used immediately with existing OSHW carriers like AFC/AFCK. > > AFCK may be overkill. We are still working on evaluating the FPGA resource > requirements. > > > - it could be hard to fit FPGA, supply, DACs and several RF modules, > > all on single dual width AMC, especially when shielding is required. > > RTM relaxes these constraints > > - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF > > modules. In case of single AMC board it would be hard to achieve such > > channels density. > > How about this: > * we reduce the number of channels per AMC to 4 DACs + 4 ADCs > * we can therefore use a smaller FPGA. Communication lanes to the master > board are relatively cheap if we put them on IOSERDES. > * the power density and cooling requirements are also reduced. > * for the RF daughter cards, we use a custom form factor that can use at > least > 2/3 of the AMC front panel > * connectors between the DSP card and the RF daughter card are 2mm header > and 8x SMP > * the rest of the AMC front panel used for (optional, runtime selectable) > clock input and some TTLs. > > Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
