Thank you for the detailed study Robert.
> This setup can -- for example -- generate a two-tone signal at 162 MHz > and 238 MHz by setting f0=157 MHz, f1=5 MHz, f2=81 MHz. The attached > plot has the data and the spectrum from a bit-accurate simulation of > the full FPGA gateware. Units are "natural" (sample rate=1, full > scale=1): the relevant tones are close to 0.1 and 0.15 sample rate. > Output amplitude is below clipping. > Thank you for the specific example. > * 200 MHz is a bit under maximum achievable speed for this logic on a > -2 speed grade kintex 7. > Can -1 speed grade on UltraScale handle generation at the 1 Gb/s data rate ? > * 1.6 GHz * 4 channels is more than we can push to a DAC. The design > can obviously also run at 1 GHz (f1,f2 at 125 MHz, f0 at 1 GHz) which > would just about fill eight JESD204B pipes. > That is, e Each DAC requires 2 parallel JESD channels at 10 Gb/s. * The design can also be built for 800 MHz with significantly lower > resource usage (then running the f1,f2 NCOs at 200 MHz, f0 at 4*200 > MHz = 800 MHz). This would free a lot of room on the FPGA, fit the > JESD pipes, and would still be able to comfortably generate the signal > above. > > This demonstrates that we can actually get very good high-data-rate > two-tone signals for eight channels out of gateware that fits on > currently available development boards. Splendid! This leaves room for future room for features like PID. -Joe
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