How about all of that code written before 64 bit z. I had stuff as old as 1985 still running in 2017.
Laddie Hanus Sent from whatever device I am using. > On Nov 30, 2021, at 12:22 PM, Mark Hammack <mark.hamm...@gmail.com> wrote: > > If the caller only passes a 72 byte save area (rather than part of a larger > save area stack) then I've got bigger problems than how to test and/or set > c'F4SA' in the save area. :-) > > > *Mark* > > >> On Tue, Nov 30, 2021 at 12:14 PM Seymour J Metz <sme...@gmu.edu> wrote: >> >> You could certainly do a normal STM R14,R12,12(R13); 4(R13) is normally >> the back point for 24-bit linkage. >> >> The 72-byte SA only has 15 words left at offset 12; that's not enough for >> that STGM, so you need to test first. >> >> -- >> Shmuel (Seymour J.) Metz >> http://mason.gmu.edu/~smetz3 >> >> ________________________________________ >> From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on >> behalf of Mark Hammack [mark.hamm...@gmail.com] >> Sent: Tuesday, November 30, 2021 12:43 PM >> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >> Subject: Re: Base-less macros >> >> Couldn't do a "normal" STM R14,R12,4(R13) since that would overlay the area >> to be checked. STGM 14,12,8(13) would probably work in most cases. Either >> the first 72 bytes will be rewritten with the STM or the data is already >> stored. The only issue I see is possibly debugging, trying to decipher the >> RSA chain to figure out what routine was called prior to the current >> routine (had to do that a couple of times). >> >> >> >> *Mark* >> >> >> On Tue, Nov 30, 2021 at 10:13 AM Charles Mills <charl...@mcn.org> wrote: >> >>>> the caller must provide a large enough area to allow for the 144 byte >>> >>> Does that not make the problem go away? Simply automatically always save >>> the low order halves of the registers, and if the subroutine will be >>> altering the high halves, save those also. Done. The *caller* has no say >> in >>> the save area format. >>> >>> Charles >>> >>> >>> -----Original Message----- >>> From: IBM Mainframe Assembler List [mailto: >> ASSEMBLER-LIST@LISTSERV.UGA.EDU] >>> On Behalf Of Mark Hammack >>> Sent: Tuesday, November 30, 2021 7:54 AM >>> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >>> Subject: Re: Base-less macros >>> >>> In our case, the caller doesn't "know" whether the called subroutine is >>> base 31 or base 64. So it is up to the called subroutine to "figure out" >>> whether the caller used a 72 byte save area or a 144 byte save area. >>> Parameters to the macro set addressing mode, RSA size, etc. This allows >>> for a 31 bit module to call a 64 bit subroutine and vice versa. That's >>> what I really mean by "switches between". The one caveat is that the >>> caller must provide a large enough area to allow for the 144 byte area. >>> >>> Since some subroutines accept arguments in R0 and/or R1 (and >> unfortunately >>> assume other registers are pre-loaded) those can't be touched before >> being >>> saved. Likewise, if the routine is called from another 64 bit >> subroutine, >>> the high halves of registers are (potentially) in use. However, since >>> (currently) all of our programs run below the bar, using the high half of >>> R14 may be an option. I need to look into using a FPR or AR but the 4 >> byte >>> literal pool works for now. Storing R14 in 8(R13) is not a bad idea >>> either. >>> >>
