You say that you want the instruction in a SETC, so presumably it might also be in 2, one for the opcode (SR in this case) and the other for the register?
-----Oprindelig meddelelse----- Fra: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> På vegne af João Reginato Sendt: 14. november 2023 22:37 Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU Emne: Re: ASMA057E Undefined operation code SR 15,15 yes, it worked too, but I still can't understand why. Maybe a bug? Em ter., 14 de nov. de 2023 às 18:31, Willy Jensen < willy.h.jen...@outlook.com> escreveu: > You still have one veriable set to 2 components. > This works: > > Macro > ZERO &N > lclc &p1(2) > &p(1) setc 'SR' > &p(2) setc '&n' > &p(1) &p(2),&p(2) > Mend > > -----Oprindelig meddelelse----- > Fra: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> På > vegne af João Reginato > Sendt: 14. november 2023 22:27 > Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Emne: Re: ASMA057E Undefined operation code SR 15,15 > > sublisted the same: > > Loc Object Code Addr1 Addr2 Stmt Source Statement > HLASM R6.0 2023/11/14 18.26 > 1 MACRO > > 2 &NAME ZERO &N > > 3 LCLC &INS(2) > > 4 &INS(1) SETC 'SR ' > > 5 &INS(2) SETC ' &N,&N' > > 6 &NAME &INS(1).&INS(2) > > 7 MEND > > 000000 00000 00000 8 XYZ CSECT > > 9 ABC ZERO 15 > > 10+ABC SR 15,15 > 01-00006 > ** ASMA057E Undefined operation code - 00006/SR 15,15 > > ** ASMA435I Record 6 in JOAO.QWASM.JOB09587.D0000101.? on volume: > > 11 END > > > > > Em ter., 14 de nov. de 2023 às 18:25, João Reginato > <jb.regin...@gmail.com > > > escreveu: > > > same error with 2 variables: > > > > Loc Object Code Addr1 Addr2 Stmt Source Statement > > HLASM R6.0 2023/11/14 18.23 > > 1 MACRO > > > > 2 &NAME ZERO &N > > > > 3 LCLC &INS1,&INS2 > > > > 4 &INS1 SETC 'SR ' > > > > 5 &INS2 SETC ' &N,&N' > > > > 6 &NAME &INS1.&INS2 > > > > 7 MEND > > > > 000000 00000 00000 8 XYZ CSECT > > > > 9 ABC ZERO 15 > > > > 10+ABC SR 15,15 > > 01-00006 > > ** ASMA057E Undefined operation code - 00006/SR 15,15 > > > > ** ASMA435I Record 6 in JOAO.QWASM.JOB09586.D0000101.? on volume: > > > > > > > > Em ter., 14 de nov. de 2023 às 18:20, Willy Jensen < > > willy.h.jen...@outlook.com> escreveu: > > > >> Would a sublisted SETC do, where P(1) is the instruction and P(2) > >> is the register? > >> > >> -----Oprindelig meddelelse----- > >> Fra: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> > >> På vegne af João Reginato > >> Sendt: 14. november 2023 22:16 > >> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU > >> Emne: Re: ASMA057E Undefined operation code SR 15,15 > >> > >> without the SETC it works but I need it to simplify the logic of a > >> bigger macro. > >> . > >> João Reginato > >> (61) 9911-55500 > >> > >> > >> Em ter., 14 de nov. de 2023 às 18:08, Paul Gilmartin < > >> 00000014e0e4a59b-dmarc-requ...@listserv.uga.edu> escreveu: > >> > >> > On 11/14/23 13:58:30, João Reginato wrote: > >> > > Gil > >> > > > >> > > I know it works in the way you've proposed but I need to use > >> > > the SETC in > >> > a > >> > > very bigger macro. > >> > >. > >> > Please post an example showing the failure without the SETC. > >> > > >> > Would it be better to have two separate MACROs, one of which > >> > calls the other? > >> > > >> > >> Em ter., 14 de nov. de 2023 às 17:46, Paul Gilmartin escreve:>>>> . > >> > >>> I believe the SETC is unnecessary. How a bout just: > >> > >>> MACRO > >> > >>> &REST ZERO &N > >> > >>> &REST SR &N,&N > >> > >>> MEND > >> > >>> > >> > >>> START > >> > >>> L ZERO 15 > >> > >>> END > >> > > >> > -- > >> > gil > >> > > >> > > >
