Hi Aditya
I think by changing PLL control register setting u sud b able to achieve your
goal.(also u will require som sw changes)
look in reg.h of ath5k
/*
* PHY PLL (Phase Locked Loop) control register
*/
#define AR5K_PHY_PLL 0x987c
#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */
i have never done this bt its my understanding that this is the way.
FULLRATE 40 MHz core clock BW = 20Mhz
HALF_RATE 20 MHz core clock BW = 10Mhz
QUARTER_RATE 10 MHz core clock BW = 5Mhz
u sud also check legacy or Sams HAL for a better understanding.
Hope this helps
Shashi
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