seanadams Wrote: > > I've done a great deal of experimentation with clock jitter recently > using more advanced tools, and I suspect (thought I haven't tested this > particular case yet) that the clock embdedding/recovery mechanism of > s/pdif is a red herring, at least for a well designed system with good > cables and clean power. I suspect the biggest issue is the noise in the > transceivers and on the cable itself, not some inherent sloppiness in > the manchester encoding/recovery process. If this is true, then > separating clock and data would not address this at all in EITHER case. > Only reversing the direction of the clock (by a word clock line, for > example) would address this, by confining the "important" clock to a > small domain very close to the DAC.
Interesting. My understanding was that a primary concern is avoiding jitter correlated with the data signal, since uncorrelated jitter (due to thermal noise for example) is pretty white and typically just adds a bit to the noise floor. It certainly seems that isolating the clock and data lines should help with avoiding such correlations. I've seen examples, such as figure 9 here http://www.stereophile.com/reference/1093jitter/index2.html, where you can clearly see a spike in the jitter spectrum due to correlations with the digital signal. It would be interesting to see if an I2S implementation would get rid of that or not. How is the I2S connection to the internal DAC in the SB3 implemented? -- opaqueice ------------------------------------------------------------------------ opaqueice's Profile: http://forums.slimdevices.com/member.php?userid=4234 View this thread: http://forums.slimdevices.com/showthread.php?t=24732 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
