Phil Leigh;502039 Wrote: > The more I think about it the less sense the "cpu working harder=more > noise=more jitter" theory makes to me. > > Surely this would be measurable using a jitter analyser?
The mechanism would be noise on the power supply internal to the FPGA. Variations of supply voltage do affect gate timing, and we have to allow for this when designing chips. If I recall Sean's description of the touch's spdif circuitry correctly though, there's a retiming flop, external to the FPGA isn't there? It would greatly reduce, if not eliminate, this source of jitter. And yes, there's no reason that this can't be measured and put to bed! -- DCtoDaylight Audiophile wish list: Zero Distortion, Infinite Signal to Noise Ratio, and a Bandwidth from DC to Daylight ------------------------------------------------------------------------ DCtoDaylight's Profile: http://forums.slimdevices.com/member.php?userid=7284 View this thread: http://forums.slimdevices.com/showthread.php?t=71321 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/mailman/listinfo/audiophiles
