DCtoDaylight;502075 Wrote: > The mechanism would be noise on the power supply internal to the FPGA. > Variations of supply voltage do affect gate timing, and we have to allow > for this when designing chips. If I recall Sean's description of the > touch's spdif circuitry correctly though, there's a retiming flop, > external to the FPGA isn't there? It would greatly reduce, if not > eliminate, this source of jitter. > > And yes, there's no reason that this can't be measured and put to bed!
ah - I see... internal to the FPGA - good point. Thanks, DC. That would difficult to measure directly? I think John Swenson mentioned something about that FLOP... I'll have to look back at his posts! -- Phil Leigh You want to see the signal path BEFORE it gets onto a CD/vinyl...it ain't what you'd call minimal... SB Touch Beta (wired) - TACT 2.2X (Linear PSU) + Good Vibrations S/W - MF Triplethreat(Audiocom full mods) - Linn 5103 - Aktiv 5.1 system (6x LK140's, ESPEK/TRIKAN/KATAN/SEIZMIK 10.5), Townsend Supertweeters, Blue Jeans Digital,Kimber Speaker & Chord Interconnect cables Kitchen Boom, Outdoors: SB Radio ------------------------------------------------------------------------ Phil Leigh's Profile: http://forums.slimdevices.com/member.php?userid=85 View this thread: http://forums.slimdevices.com/showthread.php?t=71321 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/mailman/listinfo/audiophiles
