On Tue, 19 Jul 2011 01:15:27 +0200 Rafał Miłecki <[email protected]> wrote:
> > No. The _DMA_ interrupt masks. Each DMA engine has its interrupt mask > > register. > > You must mean descriptors, sorry, I misunderstood you. Ehm, no? I mean the DMA interrupt mask registers: #define B43_MMIO_DMA0_IRQ_MASK 0x24 #define B43_MMIO_DMA1_IRQ_MASK 0x2C #define B43_MMIO_DMA2_IRQ_MASK 0x34 #define B43_MMIO_DMA3_IRQ_MASK 0x3C #define B43_MMIO_DMA4_IRQ_MASK 0x44 #define B43_MMIO_DMA5_IRQ_MASK 0x4C _______________________________________________ b43-dev mailing list [email protected] http://lists.infradead.org/mailman/listinfo/b43-dev
