Hello TJF,

Thanks for your suggestion, to clarify my side further, let me elaborate.


My requirement is 256 (samples per Cycle) * 50(cycles, power frequency) * 6
(channels) = 76.8 k SPS

So I need overall 100k(rounded off) 100k sampling.

And my input signal is between +- 10 Volts and I don't want to scale for
resolution purposes. Apart from that I need dedicated ADC for each channels
so I'll prefer separate ADC chip.
Does this make sense? Or I am wrong?

Thanks

On Friday, April 14, 2017, TJF <jeli.freih...@gmail.com> wrote:

> Hi Rathin!
>
> Am Freitag, 14. April 2017 16:58:58 UTC+2 schrieb Rathin Dholakia:
>>
>> I am willing to interface, 12 bit 4 channel, Simultaneous Sampling
>> High-Speed ADC (Analog AD7864
>> <http://www.analog.com/media/en/technical-documentation/data-sheets/AD7864.pdf>)
>> to BeagleBone Black, and operate it at 100k sampling rate. My present
>> thoughts are to use header P8 Digital I/O pins to control the ADC as well
>> as to read the input data from the ADC (using interrupt(s) - EOC). I will
>> also do a DFT on the received data samples.
>>
>
> Your target isn't very clear. Do you mean 100 k overall sampling rate (2 x
> 25 k)? In this case you could use the internal ADC (up to 4 x 50 k sampling
> rate, 0-1V8). Otherwise you'll need the external.
>
> Anyway, it should be possible when you fetch the samples by one PRU, and
> use the other for DFT. Slow tasks can run on the ARM under Linux.
>
> Regards
>
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-- 
Rathin A. Dholakia
"Dont GO through life, GROW through life"

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