Dear John,

Thanks for your suggestion. Yes I was thinking in same line but bit
differently. I am still a rookie in all this so have few queries in your
approach if you can clarify.

1. Instead of PRU as oscillator, I was planning to use one of the 4 onboard
timers. Wont it be better? why didyou suggested PRU instead of Timer? some
benefit?

2. My ADC chip (AD7864) has an inbuilt ring output ring register with
circles among the outputs of 4 channels every time I pull down "READ" pin.
So, do I still need a FIFO?

3. Why SPI? wont 12 Digital parallel pin faster? and  BBB uses pin
addresses then how is DMA different from normal GPIO access?

4. For utilizing PRU, are you recommending ASM coding or normal C coding
using some library? I ham bit reluctant because of the assembly coding
involved because I am not that good at it, yet!

Thanks a ton,
Rathin

My approach in brief for people's feedback:
1. Use Timer Interrupt using on-board timer periodically for generating SOC
2. Detect EOC using interrupt from ADC, initiate read cycle (ISR) for all 4
channels
3. second interrupt watching 1PPS from GPS, which would reset the Timer
period (as disciplining sampling)
4. Use pipe for passing each buffer to DFT.
5. Use the timing info from UART to time-stamp the DFT output



On Sat, Apr 15, 2017 at 4:38 AM, John Syne <john3...@gmail.com> wrote:

> I recommend that you look for a external ADC with a sample FIFO, then the
> samples are measured at predefined intervals and you could read them with
> the ARM processor and use the PRU for your timing requirements. I take it
> you will need a disciplined oscillator sync’d to the GPS 1pps, which can be
> done with the PRU. Using an ADC with SPI interface and FIFO means you could
> use DMA to transfer the samples, freeing up the CPU for more important
> work.
>
> Regards,
> John
>
>
>
>
> On Apr 14, 2017, at 12:46 PM, Rathin Dholakia <rathindhola...@gmail.com>
> wrote:
>
> Hello TJF,
>
> Thanks for your suggestion, to clarify my side further, let me elaborate.
>
>
> My requirement is 256 (samples per Cycle) * 50(cycles, power frequency) *
> 6 (channels) = 76.8 k SPS
>
> So I need overall 100k(rounded off) 100k sampling.
>
> And my input signal is between +- 10 Volts and I don't want to scale for
> resolution purposes. Apart from that I need dedicated ADC for each channels
> so I'll prefer separate ADC chip.
> Does this make sense? Or I am wrong?
>
> Thanks
>
> On Friday, April 14, 2017, TJF <jeli.freih...@gmail.com> wrote:
>
>> Hi Rathin!
>>
>> Am Freitag, 14. April 2017 16:58:58 UTC+2 schrieb Rathin Dholakia:
>>>
>>> I am willing to interface, 12 bit 4 channel, Simultaneous Sampling
>>> High-Speed ADC (Analog AD7864
>>> <http://www.analog.com/media/en/technical-documentation/data-sheets/AD7864.pdf>)
>>> to BeagleBone Black, and operate it at 100k sampling rate. My present
>>> thoughts are to use header P8 Digital I/O pins to control the ADC as well
>>> as to read the input data from the ADC (using interrupt(s) - EOC). I will
>>> also do a DFT on the received data samples.
>>>
>>
>> Your target isn't very clear. Do you mean 100 k overall sampling rate (2
>> x 25 k)? In this case you could use the internal ADC (up to 4 x 50 k
>> sampling rate, 0-1V8). Otherwise you'll need the external.
>>
>> Anyway, it should be possible when you fetch the samples by one PRU, and
>> use the other for DFT. Slow tasks can run on the ARM under Linux.
>>
>> Regards
>>
>> --
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> --
> Rathin A. Dholakia
> "Dont GO through life, GROW through life"
>
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-- 
Rathin A. Dholakia
"Dont GO through life, GROW through life"

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