Hi Emiliano,

Debugging errors due to the axi4lite memory map can be difficult. I suggest a 
different approach before we dive too much into that.

Are you building a the platform (tutorial 1) from scratch? Or are you trying to 
compile the already completed platform tutorial file (`zcu208_tut_platform.slx` 
that can be found here: 
https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_platform). 
Try to compile this completed tutorial design. Should an issue still occur, 
this there are some other things we can look to see what may be happening. 
Hopefully, that model does compile for you though. Then, you can compare 
differences between the model file you built and what is in 
`zcu208_tut_platfrom.slx`. Should you spot differences it would be interesting 
to know what you think may be causing the problem to better catch and handle 
the limitations, or (ideally) remove the bug altogether.

Best,

Mitch

On Oct 17, 2023, at 7:54 PM, Emiliano Toledo <emilianotole...@gmail.com> wrote:

Hello, thanks everyone, I've done the proposed changes, and now doesn't get an 
error instantly, but now it seems, from what I've searched, that this new error 
related more to Vivado, mlib_devel. In particular, log file at 
"/home/casper/Desktop/tuto1_208/myproj/myproj.runs/synth_1".

Has someone encountered this error with the Toolflow?
Reposting because I think the last email got lost.

ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a 
string literal 
[/home/casper/Desktop/tuto1_208/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:94]
ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a 
string literal 
[/home/casper/Desktop/tuto1_208/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:95]
INFO: [Synth 8-2810] unit axi4lite_axi4lite_top_mmap_pkg ignored due to 
previous errors 
[/home/casper/Desktop/tuto1_208/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:67]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:02 . 
Memory (MB): peak = 2973.926 ; gain = 244.625 ; free physical = 6723 ; free 
virtual = 11392
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console 
or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Oct 13 02:51:34 2023...

Thanks again,
Emiliano


El miércoles, 11 de octubre de 2023 a las 3:21:44 UTC-3, Jack Hickish escribió:


On Tue, 10 Oct 2023, 22:46 Kaj Wiik, <kaj....@utu.fi> wrote:
Hi Jack,

This is most interesting, especially the comment "Make KRM clock SPI
work" sounds very promising!

If only I remembered what that actually referred to :)


We are using the 27DR variant but I guess the visible differences is in
RFDC only.

Have you succeeded to port casperfpga and RFDC drivers to Petalinux/Pynq?

I use casperfpga, but not pynq. But I do have a viable Linux image, which 
obviously you are welcome to.

Cheers
Jack



Thanks!

Kaj

On 11.10.2023 0.27, Jack Hickish wrote:
> Hi Kaj,
>
> I have KRM support at
> https://github.com/realtimeradio/mlib_devel/tree/souk
> <https://github.com/realtimeradio/mlib_devel/tree/souk> if that's useful.
> I've probably diverged a bit from the main mlib repo though - probably
> some of the hacks I used to support the board are no longer required now
> the rfdc block is increasingly mature
>
> Cheers
> Jack
>
> On Tue, 10 Oct 2023, 15:59 Kaj Wiik, <kjw...@utu.fi
> <mailto:kjw...@utu.fi>> wrote:
>
>     On 10.10.2023 17.32, Mitchell Burnett wrote:
>      > The `*_base.tcl` files are not being used in the toolflow for
>     RFSoC parts and so you do not need to worry about generating a new
>     base tcl file for the zcu208.
>
>     This is interesting and useful information! One file less to worry
>     about when porting the KR module :-) (which I should start next week)!
>
>     Cheers,
>     Kaj
>
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