https://github.com/AnkitDubeycs25 updated https://github.com/llvm/llvm-project/pull/169648
>From 2182c2f98a94481d3e3a539fffaf02ab2bcf5769 Mon Sep 17 00:00:00 2001 From: AnkitDubeycs25 <[email protected]> Date: Wed, 26 Nov 2025 18:17:45 +0530 Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store Intrinsics Implement CIR lowering for X86 AVX-512 compress store builtins by adding emitX86CompressStore() which emits a masked_compressstore MLIR op, wired up for all compres store builtin variants. --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 23 +++++++++++++++---- .../CodeGenBuiltins/X86/avx512vl-builtins.c | 10 ++++++++ 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 6ca8a0e7a460f..344da9a2a6e0c 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, mlir::Location loc, return maskVec; } +static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder, + mlir::Location loc, + ArrayRef<mlir::Value> ops) { + auto resultTy = cast<cir::VectorType>(ops[1].getType()); + mlir::Value maskValue = + getMaskVecValue(builder, loc, ops[2], resultTy.getSize()); + mlir::Value ptr = ops[0]; + return builder.emitIntrinsicCallOp(loc, "masked_compressstore", resultTy, + mlir::ValueRange{ops[1], ops[0], maskValue}); +} + // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins. // // The vector is split into lanes of 8 word elements (16 bits). The lower or @@ -1231,7 +1242,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_expandloadhi512_mask: case X86::BI__builtin_ia32_expandloadqi128_mask: case X86::BI__builtin_ia32_expandloadqi256_mask: - case X86::BI__builtin_ia32_expandloadqi512_mask: + case X86::BI__builtin_ia32_expandloadqi512_mask: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented X86 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return {}; + } case X86::BI__builtin_ia32_compressstoredf128_mask: case X86::BI__builtin_ia32_compressstoredf256_mask: case X86::BI__builtin_ia32_compressstoredf512_mask: @@ -1250,10 +1266,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_compressstoreqi128_mask: case X86::BI__builtin_ia32_compressstoreqi256_mask: case X86::BI__builtin_ia32_compressstoreqi512_mask: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented X86 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops); case X86::BI__builtin_ia32_expanddf128_mask: case X86::BI__builtin_ia32_expanddf256_mask: case X86::BI__builtin_ia32_expanddf512_mask: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c index e3cbc0fc10524..c280f2380cf57 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c @@ -727,3 +727,13 @@ __m256i test_mm256_maskz_load_epi64(__mmask8 __U, void const *__P) { // OGCG: @llvm.masked.load.v4i64.p0(ptr align 32 %{{.*}}, <4 x i1> %{{.*}}, <4 x i64> %{{.*}}) return _mm256_maskz_load_epi64(__U, __P); } + +void test_compress_store(void *__P, __mmask8 __U, __m128d __A) { + // CIR-LABEL: test_compress_store + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store + // OGCG: @llvm.masked.compressstore + return _mm_mask_compressstoreu_pd(__P, __U, __A); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
