https://github.com/AnkitDubeycs25 updated https://github.com/llvm/llvm-project/pull/169648
>From 15da7125da27d71389482cac29e15a2813e67a66 Mon Sep 17 00:00:00 2001 From: AnkitDubeycs25 <[email protected]> Date: Wed, 26 Nov 2025 18:17:45 +0530 Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store Intrinsics Implement CIR lowering for X86 AVX-512 compress store builtins by adding emitX86CompressStore() which emits a masked_compressstore MLIR op, wired up for all compres store builtin variants. --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 23 +++++++-- .../CodeGenBuiltins/X86/avx512vl-builtins.c | 50 +++++++++++++++++++ 2 files changed, 68 insertions(+), 5 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 6ca8a0e7a460f..b9ed2829faad3 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, mlir::Location loc, return maskVec; } +static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder, + mlir::Location loc, + ArrayRef<mlir::Value> ops) { + auto resultTy = cast<cir::VectorType>(ops[1].getType()); + mlir::Value maskValue = + getMaskVecValue(builder, loc, ops[2], resultTy.getSize()); + + return builder.emitIntrinsicCallOp(loc, "masked_compressstore", resultTy, + mlir::ValueRange{ops[1], ptr, maskValue}); +} + // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins. // // The vector is split into lanes of 8 word elements (16 bits). The lower or @@ -1231,7 +1242,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_expandloadhi512_mask: case X86::BI__builtin_ia32_expandloadqi128_mask: case X86::BI__builtin_ia32_expandloadqi256_mask: - case X86::BI__builtin_ia32_expandloadqi512_mask: + case X86::BI__builtin_ia32_expandloadqi512_mask: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented X86 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return {}; + } case X86::BI__builtin_ia32_compressstoredf128_mask: case X86::BI__builtin_ia32_compressstoredf256_mask: case X86::BI__builtin_ia32_compressstoredf512_mask: @@ -1250,10 +1266,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_compressstoreqi128_mask: case X86::BI__builtin_ia32_compressstoreqi256_mask: case X86::BI__builtin_ia32_compressstoreqi512_mask: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented X86 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops); case X86::BI__builtin_ia32_expanddf128_mask: case X86::BI__builtin_ia32_expanddf256_mask: case X86::BI__builtin_ia32_expanddf512_mask: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c index e3cbc0fc10524..019584173e3a7 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c @@ -727,3 +727,53 @@ __m256i test_mm256_maskz_load_epi64(__mmask8 __U, void const *__P) { // OGCG: @llvm.masked.load.v4i64.p0(ptr align 32 %{{.*}}, <4 x i1> %{{.*}}, <4 x i64> %{{.*}}) return _mm256_maskz_load_epi64(__U, __P); } + +void test_compress_store(void *__P, __mmask8 __U, __m128d __A) { + // CIR-LABEL: test_compress_store + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store + // OGCG: @llvm.masked.compressstore + return _mm_mask_compressstoreu_pd(__P, __U, __A); +} + +void test_compress_store_pd256(void *__P, __mmask8 __U, __m256d __A) { + // CIR-LABEL: test_compress_store_pd256 + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store_pd256 + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store_pd256 + // OGCG: @llvm.masked.compressstore + return _mm256_mask_compressstoreu_pd(__P, __U, __A); +} + +void test_compress_store_ps128(void *__P, __mmask8 __U, __m128 __A) { + // CIR-LABEL: test_compress_store_ps128 + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store_ps128 + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store_ps128 + // OGCG: @llvm.masked.compressstore + return _mm_mask_compressstoreu_ps(__P, __U, __A); +} + +void test_compress_store_epi32(void *__P, __mmask8 __U, __m128i __A) { + // CIR-LABEL: test_compress_store_epi32 + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store_epi32 + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store_epi32 + // OGCG: @llvm.masked.compressstore + return _mm_mask_compressstoreu_epi32(__P, __U, __A); +} + +void test_compress_store_epi64(void *__P, __mmask8 __U, __m128i __A) { + // CIR-LABEL: test_compress_store_epi64 + // CIR: cir.call_llvm_intrinsic "masked_compressstore" + // LLVM-LABEL: @test_compress_store_epi64 + // LLVM: @llvm.masked.compressstore + // OGCG-LABEL: @test_compress_store_epi64 + // OGCG: @llvm.masked.compressstore + return _mm_mask_compressstoreu_epi64(__P, __U, __A); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
