================
@@ -215,9 +217,35 @@ void
X86FastPreTileConfigImpl::spill(MachineBasicBlock::iterator Before,
LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
- // Don't need shape information for tile store, becasue it is adjacent to
- // the tile def instruction.
- TII->storeRegToStackSlot(*MBB, Before, VirtReg, Kill, FI, &RC, Register());
+
+ // ACE v1 doesn't have TILESTORED - use TILEMOVROW row-by-row
+ if (ST->hasACEV1() && !ST->hasAMXTILE()) {
+ const DebugLoc &DL = Before->getDebugLoc();
+ Register ScratchZMM = MRI->createVirtualRegister(&X86::VR512RegClass);
+
+ const unsigned NumRows = 16;
+ const unsigned RowSize = 64;
+
+ for (unsigned Row = 0; Row < NumRows; ++Row) {
+ // TILEMOVROW zmm, tmm, imm8 (read from tile)
+ // Only kill src on the last row read
+ bool KillSrcNow = (Row == NumRows - 1) && Kill;
+ BuildMI(*MBB, Before, DL, TII->get(X86::TILEMOVROWrti), ScratchZMM)
+ .addReg(VirtReg, getKillRegState(KillSrcNow))
+ .addImm(Row);
+
+ // VMOVUPS [stack + row*64], zmm
+ MachineInstrBuilder MIB =
+ BuildMI(*MBB, Before, DL, TII->get(X86::VMOVUPSZmr));
----------------
mahesh-attarde wrote:
I am curious what is tradeoff between VMOVUPS and VMOVDQU?
Spec did mention VMOVDQU however most avx ops are also FP32.
https://github.com/llvm/llvm-project/pull/208408
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