================
@@ -0,0 +1,417 @@
+//===---- X86InstrACE.td - ACE Instruction Set Extension --*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the ACE (AI Compute
+// Extensions) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// ACE instructions
+
+let Predicates = [HasACEV1, In64BitMode] in {
+
+// BSRINIT - Initialize Block Scale Register
+// VEX.128.F2.0F38.W1 49 11:000:000 - BSRINIT bsr0
+// BSR is implicit destination, ModRM = 11:000:000 (mod=11, reg=000, r/m=000)
+// Note: BSR0 is implicit (via Defs), not in operand list. Asm syntax has no
explicit operand.
+let SchedRW = [WriteSystem], hasSideEffects = 1, Defs = [BSR0] in {
+ def BSRINIT : I<0x49, MRM_C0, (outs), (ins),
+ "bsrinit", []>,
+ VEX, XD, T8, REX_W;
+}
+
+// BSRMOVF - Move Full to BSR
+// EVEX.512.NP.MAP6.W1 95 11:000:bbb - BSRMOVF bsr0, zmm1, zmm2/m512
+// ModRM.reg = 000 (opcode extension), EVEX.vvvv encodes zmm1, ModRM.r/m
encodes zmm2
+// BSR is implicit destination (via Defs)
+let SchedRW = [WriteVecLogic], Defs = [BSR0] in {
+ def BSRMOVFrr : I<0x95, MRM0r, (outs),
+ (ins VR512:$src1, VR512:$src2),
+ "bsrmovf\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_bsrmovf (v16i32 VR512:$src1), (v16i32
VR512:$src2))]>,
+ EVEX, T_MAP6, REX_W, EVEX_V512, VVVV;
+
+ let mayLoad = 1 in
+ def BSRMOVFrm : I<0x95, MRM0m, (outs),
+ (ins VR512:$src1, f512mem:$src2),
+ "bsrmovf\t{$src2, $src1|$src1, $src2}", []>,
+ EVEX, T_MAP6, REX_W, EVEX_V512, EVEX_CD8<64, CD8VF>, VVVV;
+}
+
+// BSRMOVH - Move Half to/from BSR
+// EVEX.512.F2.MAP6.W1 95 /r - BSRMOVH bsr0, zmm1/m512, bsr0 (load, W1)
+// EVEX.512.F2.MAP6.W0 95 /r - BSRMOVH zmm1/m512, bsr0 (store, W0)
+// BSR is implicit operand (via Defs/Uses), ModRM.reg field = 0
+// Use MRM0r/MRM0m: ModRM.reg = 0 (BSR implicit), ModRM.r/m =
source/destination
+// AsmString uses "_set"/"_get" suffix for asm matching; printer uses custom
print.
+let SchedRW = [WriteVecLogic] in {
+ // Set BSR high half (W1): BSR is both input and output (read-modify-write)
+ let Defs = [BSR0], Uses = [BSR0] in {
+ def BSRMOVHrr_set : I<0x95, MRM0r, (outs),
+ (ins VR512:$src),
+ "bsrmovh_set\t$src",
+ [(int_x86_bsrmovh_set (v16i32 VR512:$src))]>,
+ EVEX, XD, T_MAP6, REX_W, EVEX_V512;
+
+ let mayLoad = 1 in
+ def BSRMOVHrm_set : I<0x95, MRM0m, (outs),
+ (ins f512mem:$src),
+ "bsrmovh_set\t$src", []>,
+ EVEX, XD, T_MAP6, REX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
+ }
+
+ // Get BSR high half (W0): BSR is implicit source, ZMM/mem is explicit
destination
+ let Uses = [BSR0] in {
+ def BSRMOVHrr_get : I<0x95, MRM0r, (outs VR512:$dst),
+ (ins),
+ "bsrmovh_get\t$dst",
+ [(set (v16i32 VR512:$dst), (int_x86_bsrmovh_get))]>,
+ EVEX, XD, T_MAP6, EVEX_V512;
+
+ let mayStore = 1 in
+ def BSRMOVHmr_get : I<0x95, MRM0m, (outs),
+ (ins f512mem:$dst),
+ "bsrmovh_get\t$dst", []>,
+ EVEX, XD, T_MAP6, EVEX_V512, EVEX_CD8<64, CD8VF>;
+ }
+}
+
+// BSRMOVL - Move Low to/from BSR
+// EVEX.512.F3.MAP6.W1 95 /r - BSRMOVL bsr0, zmm1/m512 (load, W1)
+// EVEX.512.F3.MAP6.W0 95 /r - BSRMOVL zmm1/m512, bsr0 (store, W0)
+// BSR is implicit operand (via Defs/Uses), ModRM.reg field = 0
+// Use MRM0r/MRM0m: ModRM.reg = 0 (BSR implicit), ModRM.r/m =
source/destination
+// AsmString uses "_set"/"_get" suffix for asm matching; printer uses custom
print.
+let SchedRW = [WriteVecLogic] in {
+ // Set BSR low half (W1): BSR is both input and output (read-modify-write)
+ let Defs = [BSR0], Uses = [BSR0] in {
+ def BSRMOVLrr_set : I<0x95, MRM0r, (outs),
+ (ins VR512:$src),
+ "bsrmovl_set\t$src",
+ [(int_x86_bsrmovl_set (v16i32 VR512:$src))]>,
+ EVEX, XS, T_MAP6, REX_W, EVEX_V512;
+
+ let mayLoad = 1 in
+ def BSRMOVLrm_set : I<0x95, MRM0m, (outs),
+ (ins f512mem:$src),
+ "bsrmovl_set\t$src", []>,
+ EVEX, XS, T_MAP6, REX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
+ }
+
+ // Get BSR low half (W0): BSR is implicit source, ZMM/mem is explicit
destination
+ let Uses = [BSR0] in {
+ def BSRMOVLrr_get : I<0x95, MRM0r, (outs VR512:$dst),
+ (ins),
+ "bsrmovl_get\t$dst",
+ [(set (v16i32 VR512:$dst), (int_x86_bsrmovl_get))]>,
+ EVEX, XS, T_MAP6, EVEX_V512;
+
+ let mayStore = 1 in
+ def BSRMOVLmr_get : I<0x95, MRM0m, (outs),
+ (ins f512mem:$dst),
+ "bsrmovl_get\t$dst", []>,
+ EVEX, XS, T_MAP6, EVEX_V512, EVEX_CD8<64, CD8VF>;
+ }
+}
+
+// TILEMOVCOL - Move Column from Vector to Tile
+// EVEX.512.66.0F3A.W1 2F /r ib - TILEMOVCOL tmm1, zmm2, imm8
+// EVEX.512.66.0F38.W1 4B /r - TILEMOVCOL tmm1, zmm2, r32
+// For r32 variant: GR32 is encoded in EVEX.vvvv (use MRMSrcReg4VOp3 + VVVV)
+let SchedRW = [WriteVecLogic] in {
+ def TILEMOVCOLri : Ii8<0x2F, MRMSrcReg, (outs TILE:$dst),
----------------
mahesh-attarde wrote:
we miss out composition opportunity from existing AMXAVX512_TILEMOVE
```
multiclass AMXAVX512_TILEMOVE_SET<bits<8> Opcode1, bits<8> Opcode2, string
Opstr> {
...
}
multiclass AMXAVX512_TILEMOVE_GET<bits<8> Opcode1, bits<8> Opcode2, string
Opstr> {
...
}
defm TILEMOVROW : AMXAVX512_TILEMOVE_SET<0x07, 0x4A, "tilemovrow">,
AMXAVX512_TILEMOVE_SGT<0x07, 0x4A, "tilemovrow">, ;
defm TILEMOVCOL : AMXAVX512_TILEMOVE_GET<0x08, 0x5A, "tilemovcol">;
```
https://github.com/llvm/llvm-project/pull/208408
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
