llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: TelGome <details> <summary>Changes</summary> This pr support RISC-V P extension intrinsics [Packed "Q-format" Multiply Parts Accumulate](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-q-format-multiply-parts-accumulate) --- Patch is 66.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/217918.diff 11 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+22) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+82) - (modified) clang/lib/Headers/riscv_packed_simd.h (+27-5) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+388) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+126) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+25) - (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+16) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+211) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+122) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+96) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+177) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index b91b356d7a25d..19b5ef48215f8 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -297,6 +297,28 @@ def pmulqr_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, def pmulq_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; def pmulqr_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; +// Packed "Q-format" Multiply Parts Accumulate (32-bit) +def mqacc_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def mqacc_h01_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def mqacc_h11_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def mqracc_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def mqracc_h01_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def mqracc_h11_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; + +// Packed "Q-format" Multiply Parts Accumulate (64-bit) +def pmqacc_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmqacc_h01_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmqacc_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmqracc_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmqracc_h01_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmqracc_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def mqacc_w00_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def mqacc_w01_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def mqacc_w11_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def mqracc_w00_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def mqracc_w01_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def mqracc_w11_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; + // Packed Sign and Zero Extend (32-bit) def psext_b_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">; def pzext_b_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index eb98b38974b21..2845388ebbece 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1544,6 +1544,88 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; } + // Packed "Q-format" Multiply Parts Accumulate + case RISCV::BI__builtin_riscv_mqacc_h00_i32: + case RISCV::BI__builtin_riscv_mqacc_h01_i32: + case RISCV::BI__builtin_riscv_mqacc_h11_i32: + case RISCV::BI__builtin_riscv_mqracc_h00_i32: + case RISCV::BI__builtin_riscv_mqracc_h01_i32: + case RISCV::BI__builtin_riscv_mqracc_h11_i32: + case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2: + case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2: + case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2: + case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2: + case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2: + case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2: + case RISCV::BI__builtin_riscv_mqacc_w00_i64: + case RISCV::BI__builtin_riscv_mqacc_w01_i64: + case RISCV::BI__builtin_riscv_mqacc_w11_i64: + case RISCV::BI__builtin_riscv_mqracc_w00_i64: + case RISCV::BI__builtin_riscv_mqracc_w01_i64: + case RISCV::BI__builtin_riscv_mqracc_w11_i64: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_mqacc_h00_i32: + ID = Intrinsic::riscv_mqacc_h00; + break; + case RISCV::BI__builtin_riscv_mqacc_h01_i32: + ID = Intrinsic::riscv_mqacc_h01; + break; + case RISCV::BI__builtin_riscv_mqacc_h11_i32: + ID = Intrinsic::riscv_mqacc_h11; + break; + case RISCV::BI__builtin_riscv_mqracc_h00_i32: + ID = Intrinsic::riscv_mqracc_h00; + break; + case RISCV::BI__builtin_riscv_mqracc_h01_i32: + ID = Intrinsic::riscv_mqracc_h01; + break; + case RISCV::BI__builtin_riscv_mqracc_h11_i32: + ID = Intrinsic::riscv_mqracc_h11; + break; + case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2: + ID = Intrinsic::riscv_pmqacc_h00; + break; + case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2: + ID = Intrinsic::riscv_pmqacc_h01; + break; + case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2: + ID = Intrinsic::riscv_pmqacc_h11; + break; + case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2: + ID = Intrinsic::riscv_pmqracc_h00; + break; + case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2: + ID = Intrinsic::riscv_pmqracc_h01; + break; + case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2: + ID = Intrinsic::riscv_pmqracc_h11; + break; + case RISCV::BI__builtin_riscv_mqacc_w00_i64: + ID = Intrinsic::riscv_mqacc_w00; + break; + case RISCV::BI__builtin_riscv_mqacc_w01_i64: + ID = Intrinsic::riscv_mqacc_w01; + break; + case RISCV::BI__builtin_riscv_mqacc_w11_i64: + ID = Intrinsic::riscv_mqacc_w11; + break; + case RISCV::BI__builtin_riscv_mqracc_w00_i64: + ID = Intrinsic::riscv_mqracc_w00; + break; + case RISCV::BI__builtin_riscv_mqracc_w01_i64: + ID = Intrinsic::riscv_mqracc_w01; + break; + case RISCV::BI__builtin_riscv_mqracc_w11_i64: + ID = Intrinsic::riscv_mqracc_w11; + break; + } + + IntrinsicTypes = {ResultType, Ops[1]->getType()}; + break; + } + // Zk builtins // Zknh diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 491e219bec297..0d46b0200dca9 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -261,7 +261,7 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return builtin(__rs1, __rs2); \ } -#define __packed_abdsum_acc(name, rty, ty, builtin) \ +#define __packed_ternary_builtin(name, rty, ty, builtin) \ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty __rs1, \ ty __rs2) { \ return builtin(__rd, __rs1, __rs2); \ @@ -744,13 +744,13 @@ __packed_binary_builtin_mixed(pmulhrsu_i32x2, int32x2_t, int32x2_t, uint32x2_t, /* Packed Absolute Difference Sum (32-bit) */ __packed_abdsum(pabdsumu_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumu_u8x4_u32) -__packed_abdsum_acc(pabdsumau_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumau_u8x4_u32) +__packed_ternary_builtin(pabdsumau_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumau_u8x4_u32) /* Packed Absolute Difference Sum (64-bit) */ __packed_abdsum(pabdsumu_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pabdsumu_u8x8_u32) __packed_abdsum(pabdsumu_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumu_u8x8_u64) -__packed_abdsum_acc(pabdsumau_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u32) -__packed_abdsum_acc(pabdsumau_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u64) +__packed_ternary_builtin(pabdsumau_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u32) +__packed_ternary_builtin(pabdsumau_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u64) /* Packed Saturating Absolute Value (32-bit) */ __packed_unary_builtin(psabs_i8x4, int8x4_t, __builtin_riscv_psabs_i8x4) @@ -781,6 +781,28 @@ __packed_binary_builtin(pmulqr_i16x4, int16x4_t, __builtin_riscv_pmulqr_i16x4) __packed_binary_builtin(pmulq_i32x2, int32x2_t, __builtin_riscv_pmulq_i32x2) __packed_binary_builtin(pmulqr_i32x2, int32x2_t, __builtin_riscv_pmulqr_i32x2) +/* Packed "Q-format" Multiply Parts Accumulate (32-bit) */ +__packed_ternary_builtin(mqacc_h00_i32, int, int16x2_t, __builtin_riscv_mqacc_h00_i32) +__packed_ternary_builtin(mqacc_h01_i32, int, int16x2_t, __builtin_riscv_mqacc_h01_i32) +__packed_ternary_builtin(mqacc_h11_i32, int, int16x2_t, __builtin_riscv_mqacc_h11_i32) +__packed_ternary_builtin(mqracc_h00_i32, int, int16x2_t, __builtin_riscv_mqracc_h00_i32) +__packed_ternary_builtin(mqracc_h01_i32, int, int16x2_t, __builtin_riscv_mqracc_h01_i32) +__packed_ternary_builtin(mqracc_h11_i32, int, int16x2_t, __builtin_riscv_mqracc_h11_i32) + +/* Packed "Q-format" Multiply Parts Accumulate (64-bit) */ +__packed_ternary_builtin(pmqacc_h00_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqacc_h00_i32x2) +__packed_ternary_builtin(pmqacc_h01_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqacc_h01_i32x2) +__packed_ternary_builtin(pmqacc_h11_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqacc_h11_i32x2) +__packed_ternary_builtin(pmqracc_h00_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqracc_h00_i32x2) +__packed_ternary_builtin(pmqracc_h01_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqracc_h01_i32x2) +__packed_ternary_builtin(pmqracc_h11_i32x2, int32x2_t, int16x4_t, __builtin_riscv_pmqracc_h11_i32x2) +__packed_ternary_builtin(mqacc_w00_i64, int64_t, int32x2_t, __builtin_riscv_mqacc_w00_i64) +__packed_ternary_builtin(mqacc_w01_i64, int64_t, int32x2_t, __builtin_riscv_mqacc_w01_i64) +__packed_ternary_builtin(mqacc_w11_i64, int64_t, int32x2_t, __builtin_riscv_mqacc_w11_i64) +__packed_ternary_builtin(mqracc_w00_i64, int64_t, int32x2_t, __builtin_riscv_mqracc_w00_i64) +__packed_ternary_builtin(mqracc_w01_i64, int64_t, int32x2_t, __builtin_riscv_mqracc_w01_i64) +__packed_ternary_builtin(mqracc_w11_i64, int64_t, int32x2_t, __builtin_riscv_mqracc_w11_i64) + /* Packed Narrowing Clip Pair (32-bit) */ __packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4) __packed_binary_builtin_cast(pnclipup_u8x4, uint16x2_t, uint8x4_t, __builtin_riscv_pnclipup_u8x4) @@ -937,7 +959,7 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_nziph2 #undef __packed_nziph4 #undef __packed_abdsum -#undef __packed_abdsum_acc +#undef __packed_ternary_builtin #undef __packed_reinterpret #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index d6afc4d18cc6a..d840a668d9f92 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -9705,3 +9705,391 @@ int32x2_t test_pnclipp_i32x2(int64_t rs1, int64_t rs2) { uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { return __riscv_pnclipup_u32x2(rs1, rs2); } + +/* Packed "Q-format" Multiply Parts Accumulate (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_mqacc_h00_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqacc_h00_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// + +int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqacc_h00_i32(rd, rs1, rs2); +} +// RV32-LABEL: define dso_local i32 @test_mqacc_h01_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqacc_h01_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// +int32_t test_mqacc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqacc_h01_i32(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mqacc_h11_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqacc_h11_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// +int32_t test_mqacc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqacc_h11_i32(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mqracc_h00_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqracc_h00_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// +int32_t test_mqracc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqracc_h00_i32(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mqracc_h01_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqracc_h01_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// +int32_t test_mqracc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqracc_h01_i32(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mqracc_h11_i32( +// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local signext i32 @test_mqracc_h11_i32( +// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: ret i32 [[TMP2]] +// +int32_t test_mqracc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_mqracc_h11_i32(rd, rs1, rs2); +} + +/* Packed "Q-format" Multiply Parts Accumulate (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pmqacc_h00_i32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]]) +// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// RV32-NEXT: ret i64 [[TMP4]] +// +// RV64-LABEL: define dso_local i64 @test_pmqacc_h00_i32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]]) +// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// RV64-NEXT: ret i64 [[TMP4]] +// +int32x2_t test_pmqacc_h00_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) { + return __riscv_pmqacc_h00_i32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pmqacc_h01_i32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]]) +// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// RV32-NEXT: ret i64 [[TMP4]] +// +// RV64-LABEL: define dso_local i64 @test_pmqacc_h01_i32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_C... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/217918 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
