================
@@ -2739,6 +2754,64 @@ let append Predicates = [IsRV64] in {
def : Pat<(v2i32 (riscv_pnclipup_w GPR:$rs1, GPR:$rs2)),
(PNCLIPUP_W GPR:$rs1, GPR:$rs2)>;
+ // Packed "Q-format" multiply parts accumulate
+ def : Pat<(v2i32 (riscv_pmqacc_h00 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQACC_W_H00 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmqacc_h01 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQACC_W_H01 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmqacc_h11 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQACC_W_H11 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmqracc_h00 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQRACC_W_H00 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmqracc_h01 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQRACC_W_H01 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmqracc_h11 (v2i32 GPR:$rd),
+ (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMQRACC_W_H11 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+
+ def : Pat<(XLenVT (riscv_mqacc_w00 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQACC_W00 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVT (riscv_mqacc_w01 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQACC_W01 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVT (riscv_mqacc_w11 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQACC_W11 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVT (riscv_mqracc_w00 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQRACC_W00 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVT (riscv_mqracc_w01 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQRACC_W01 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVT (riscv_mqracc_w11 (XLenVT GPR:$rd),
+ (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))),
+ (MQRACC_W11 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+
+ def : Pat<(XLenVT (riscv_pmqacc_w_h00 (XLenVT GPR:$rd),
----------------
TelGome wrote:
Done. Dropped the second set of SDNodes/Patterns (`riscv_pmqacc_w_h*`) and the
`getRVPQFormatAccWideOpcode` helper. The i32-result RV64 form now reuses the
existing `riscv_pmqacc_h00` packed-halfword SDNode: in `ReplaceNodeResults`,
widen rd to v2i32 with `getBuildVector(v2i32, {rd, undef})` and each v2i16
source to v4i16 with `CONCAT_VECTORS(v2i16, undef)` (upper lanes undef since
only the low lane contributes to the i32 result), emit `riscv_pmqacc_h00` →
v2i32, then `getExtractVectorElt` to take the low element.
https://github.com/llvm/llvm-project/pull/217918
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