================
@@ -3062,3 +2951,99 @@ define <2 x i16> @test_pnclipup_v2i16(i32 %a, i32 %b) {
%r = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 %a, i32 %b)
ret <2 x i16> %r
}
+
+define i32 @test_mqacc_h00_i32(i32 %rd, <2 x i16> %a, <2 x i16> %b) {
+; RV32-LABEL: test_mqacc_h00_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mqacc.h00 a0, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_mqacc_h00_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: zext.w a2, a2
----------------
TelGome wrote:
Done. The zext.w was a side effect of zero-extending the v2i16 source to fill
the upper half of the 64-bit register. Switched to undef fill (CONCAT_VECTORS
with UNDEF) for the upper lanes, so zext.w is no longer emitted. The i32-result
RV64 form is now pmv.ws + pmqacc.w.hXX.
https://github.com/llvm/llvm-project/pull/217918
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