hi,
comments in-line: -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On Behalf Of Howard C. Berkowitz Sent: Wednesday, February 19, 2003 2:17 PM To: [EMAIL PROTECTED] Subject: RE: Does MLS (Layer 3 switching) require VLANs? [7:63147] At 6:51 PM +0000 2/19/03, Vicky Rode wrote: >comments in-line: > > >-----Original Message----- >From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On Behalf Of >Howard C. Berkowitz >Sent: Tuesday, February 18, 2003 6:42 AM >To: [EMAIL PROTECTED] >Subject: Re: Does MLS (Layer 3 switching) require VLANs? [7:63147] > > >At 5:30 AM +0000 2/18/03, Ken Diliberto wrote: >>The nit I'm picking is inline... (I'm feeling like chipping in tonight) >> >>>>> "The Long and Winding Road" >>02/17/03 06:13PM >>> >> >>[snip] >> >>if I have a 75xx router with 300 ethernet ports, and I bridge all >>those >>ports, do I have an L3 switch, or a router? >> >>[KD] >>You have a router performing L2 operations (forwarding, switching, >>bridging -- whatever). Would a cheap Linksys switch be faster? >> >>What makes a L3 switch in my mind is where the forwarding happens. If >>the L3 CPU (new way to look at it?) has to handle every packet, that's a >>router. If the first L3 packet is handled by the CPU which then >>programs ASICs to handle the rest of the flow without bothering the CPU, >>that's an L3 switch. Is there a difference from a packet/network >>perspective? No. The L2 headers and L3 headers are all properly >>updated in both cases (at least we *hope* they are) and traffic is >>delivered most of the time. (If it was delivered all the time, networks >>wouldn't need us to fix them) :-) > >Does that make a 7500 with VIPs a L3 switch? A 12000 with >distributed forwarding processors? >------------------------------ >it depends....call it (d)cef switching router if you want but i have to >kinda agree with ken's comments. in my opinion the major difference between >a tradition router and a l3 switch is the way packet switching takes place. >in a tradition router the packet switching are done in software >(microprocessor based), Big difference if the microprocessors (note plural) aren't doing anything except forwarding, and run a real time OS. The key thing is that you don't want forwarding going through the processor that runs routing protocols, system management, etc. -------------------------vicky> true enough. but in my opinion it depends on what hw you have in play and for what purpose. whether it is going to be classic line cards, switch fabric cards or distributed forwarding cards and whether the packet switching is going to be flow based or cef based. i guess one should have a good understanding for what their network traffic looks like and a good baseline before retrofitting to high powered hw which can be a big waste of money and resources. A real challenge is where to implement QoS, because it tends to get beyond the complexity of a true ASIC and really has to be done in a microcode-loaded processor. ----------------------vicky> for me polling and gathering different qos snmp data variables has been a challenge rather than hw issue, so i can't really comment on that. >whereas in l3 switch it is done by asic in hw and >mls is used to increase routing performance by doing packet switching and >rewrites in hw (asics). There's a bit of Cisco marketing-speak here, which was actually a reaction to competitors who brought up the concept "switch if you can, route when you must." Hardware and software technology have moved on since then, and the line is much more blurred between the two. It's more important to think of separating the forwarding, control, and upper layer services path (and being sure there's no mutual interference) than it is to consider the actual hardware processing elements (ASICs, microcoded or RISC processors, etc.) -----------------------vicky> in my opinion, what's important and necessary is control/forward plane inter-relation. that's all. regards, /vicky This emphasis on ASICs also ignores a couple of common bottlenecks: memory and fabric. To some extent, you can get around memory limitations by having distributed memories for distributed processors. For the fabric, you can move from shared bus, to shared memory, and eventually to crossbar (ignoring optical trends). As I mentioned in a previous post that's partially below, you don't necessarily need ASICs if you have enough distributed processors, using the term "processor" to include microcode sequencers, FPGAs and EA-FPGAs, etc. In research prototypes, I've been involved in routers that had true processors, running on the forwarding boards, that ran a real-time OS. These processors did have certain functions custom-built in hardware. Also, the processors can have coprocessors -- the Nortel Shasta products, for example, have an encryption chip more or less next to general board-level processors, with a high-speed path between them. Even with ASICs, the L2 and L3 decisions, rewrite, etc. often are in separate chips. Remember a processor can be implemented as bit slices operating in a set of ICs. > > > >Substituting router for L3 switch is a good idea, but go farther than >that. You can think of a high-performance router as a small hidden >network, containing one or more (think high availability) path >determination "routing" processors/hosts that download FIB >information to multiple forwarding processors/hosts. One public and >vendor-independent discussion of this architecture continues in the >IETF FORCES Working Group (go to www.ietf.org and navigate to Working >Groups). > >> >>What does this mean to us? Not much other than for capacity planning. >>IMHO, an L3 switch has a longer life than a router. > >Not really, as you say in your next paragraph. I could go off into >the ozone and say all high-speed routers are L3 switches. > >Indeed, ASICs aren't a necessity. I've worked on research router >designs that used RISC processors in each forwarding and path >determination engine, which gave lots of power but much more >flexibility than ASICs. Admittedly, at least one of these was a >specifically designed processor, but it definitely was software >loadable and ran a real time OS. ASIC gets blurry anyway, when you >start getting into the pure hard-etched IC, field-programmable gate >arrays, electrically alterable field-programmable gate arrays, >microcode sequencers, etc. > >> >>When I design networks, I don't think L3 switch. I think about routers >>interconnecting L2 segments. I even draw them that way most of the >>time. :-) >> >>My advice to those having problems with this subject: Replace every >>occurrence of "layer 3 switch" with "router". >> >[/KD] Message Posted at: http://www.groupstudy.com/form/read.php?f=7&i=63406&t=63147 -------------------------------------------------- FAQ, list archives, and subscription info: http://www.groupstudy.com/list/cisco.html Report misconduct and Nondisclosure violations to [EMAIL PROTECTED]
