On Saturday 14 December 2002 09:59, Lea Gris wrote: > This is a hardware feature not a driver software implementation. 128 > bits graphic chips would have much much work addressing odd order of > bytes boundary (24bits 3 bytes) in memory even worse this would require > one more address line switch and additional logic for the RAMDAC to > decode pixels colour at an odd boundary de facto reducing decoding speed. > > If you only do 2 and 4 byte addressing you can complietely avoid using > the lower addres line, transfering data with twice and fourth the > bandwidth required by single byte addressing.
I know that seems logical. But if you think about it it isn't. The main barrier graphic hardware has is bandwidth and with a simple translation you can pack 4 pixels into 3, That is a 33% increase of bandwidth! You can claim that that needs extra hardware to be done but you have to realise that the hardware is purpose build so it probably has that hardware build in.
