You can grep for commits containing b:65442212 or b:111610455 to see the work required to remove AGESA from bootblock.
On Wed, Aug 21, 2019 at 10:22 AM Kyösti Mälkki <kyosti.mal...@gmail.com> wrote: > On Wed, Aug 21, 2019 at 6:53 PM Michal Zygowski > <michal.zygow...@3mdeb.com> wrote: > >> I get the overall idea of C bootblock. The most fun is about the > > assembly to setup CAR early. But what about S3 suspend/resume for APU2 > > for example? It is not supported by the platform and does not seem to be > > needed at all there (it is just a router which should be always on). > > Maybe the check for RELOCATABLE_RAMSTAGE should be omitted when > > HAVE_ACPI_RESUME is not set for the platform? However the thing is all > > about southbridge/northbridge code still. > > You should consider binaryPI mostly broken for the purpose of S3 > suspend/resume. I did not understand what you mean about a > RELOCATABLE_RAMSTAGE check. > > AMD never got S3 right for open-source AGESA and I think they > struggled long to get it right for amd/stoneyridge. I believe S3 > resume path is PSP assisted. When x86 core reset is deasserted some > parts of the memory controller PHY have already been programmed by PSP > or SMU firmwares. I have been told that later AGESAv5 firmwares do not > have the capability of "MRC cache" to speed up cold boot as they lack > the (x86) code to replay memory training parameters from non-volatile > memory. > > >> That stoneyridge thing is interesting... Cannot imagine what it could be > > called for such early. > > A lot of that review is public in gerrit, maybe January-March 2017. > > Regards, > Kyösti Mälkki > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org >
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