>
> I believe S3 resume path is PSP assisted. When x86 core reset is
> deasserted some parts of the memory controller PHY have already been
> programmed by PSP or SMU firmwares.
(No PSP present on the G505s)
> You should consider binaryPI mostly broken for the purpose of S3
> suspend/resume.
>
AMD never got S3 right for open-source AGESA and I think they struggled
> long to get it right for amd/stoneyridge.
Does this and the above regarding the PSP mean that S3 is impossible on the
G505s (open-source AGESA), or would otherwise require changes to the AGESA
source? (even if C_ENVIRONMENT_BOOTBLOCK were implemented? If I understand
correctly the other two requirements are already fulfilled?)
I have been told that later AGESAv5 firmwares do not have the capability of
> "MRC cache" to speed up cold boot as they lack the (x86) code to replay
> memory training parameters from non-volatile memory.
Does this apply to the G505s? I presume that it's version of AGESA predates
that used to create the PI binaries.
Sincerely,
-Matthew Bradley
On Wed, Aug 21, 2019 at 1:28 PM Kyösti Mälkki <kyosti.mal...@gmail.com>
wrote:
> On Wed, Aug 21, 2019 at 7:52 PM Raul Rangel <rran...@chromium.org> wrote:
> >
> > You can grep for commits containing b:65442212 or b:111610455 to see the
> work required to remove AGESA from bootblock.
>
> Thanks!
>
> Some of that seems very SoC or hardware specific. I think we will go
> ahead with a bootblock that does nothing else but sets up CAR and
> finds a romstage.elf to jump into. At this time verstage is not a
> requirement so we'll just ignore any LPC or SPI PAD configurations TPM
> might need.
>
> In general, changes from amd/stoneyridge do not apply to previous
> binaryPI builds. A different set of modifications to StoneyPI were
> made in comparison to the changes that SAGE had previously made to
> MullinsPI, KaveriPI and CarrizoPI. Also AMD rolled out a custom PSP
> firmware build for Chromebooks? So it is possible the implementation
> of AGESAv5 API we have for amd/stoneyridge is only compatible with the
> modified StoneyPI source tree and the modified PSP firmware. And the
> PSP mailbox APIs are not exactly the same across different SoCs
> either.
>
> Regards,
> Kyösti Mälkki
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