[edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Sunil V L]

Sstc extension allows to program the timer and receive the interrupt
without using an SBI call. This reduces the latency to generate the timer
interrupt. So, detect whether Sstc extension is supported and use the
stimecmp register directly to program the timer interrupt.

Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Andrei Warkentin <andrei.warken...@intel.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
---
 .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 ++
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 30 +++++++++++++++++--
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf 
b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index aba660186dc0..f2a2cf12caef 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -41,6 +41,7 @@ [Sources.RISCV64]
   Timer.c
 
 [Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride           ## CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
 
 [Protocols]
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h 
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 9b3542230cb5..5e5071b3f0b2 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -26,6 +26,8 @@
 //
 #define DEFAULT_TIMER_TICK_DURATION  100000
 
+#define RISCV_CPU_FEATURE_SSTC_BITMASK  0x2
+
 extern VOID
 RiscvSetTimerPeriod (
   UINT32  TimerPeriod
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c 
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index 30e48061cd06..4babfb4bfc60 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -44,6 +44,19 @@ STATIC EFI_TIMER_NOTIFY  mTimerNotifyFunction;
 STATIC UINT64  mTimerPeriod     = 0;
 STATIC UINT64  mLastPeriodStart = 0;
 
+/**
+  Check whether Sstc is enabled in PCD.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsSstcEnabled (
+  VOID
+  )
+{
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & 
RISCV_CPU_FEATURE_SSTC_BITMASK) != 0);
+}
+
 /**
   Timer Interrupt Handler.
 
@@ -94,7 +107,12 @@ TimerInterruptHandler (
                          ),
                        1000000u
                        );  // convert to tick
-  SbiSetTimer (PeriodStart);
+  if (RiscVIsSstcEnabled ()) {
+    RiscVSetSupervisorTimeCompareRegister (PeriodStart);
+  } else {
+    SbiSetTimer (PeriodStart);
+  }
+
   RiscVEnableTimerInterrupt (); // enable SMode timer int
   gBS->RestoreTPL (OriginalTPL);
 }
@@ -197,7 +215,11 @@ TimerDriverSetTimerPeriod (
                          ),
                        1000000u
                        ); // convert to tick
-  SbiSetTimer (PeriodStart);
+  if (RiscVIsSstcEnabled ()) {
+    RiscVSetSupervisorTimeCompareRegister (PeriodStart);
+  } else {
+    SbiSetTimer (PeriodStart);
+  }
 
   mCpu->EnableInterrupt (mCpu);
   RiscVEnableTimerInterrupt (); // enable SMode timer int
@@ -282,6 +304,10 @@ TimerDriverInitialize (
   //
   mTimerNotifyFunction = NULL;
 
+  if (RiscVIsSstcEnabled ()) {
+    DEBUG ((DEBUG_INFO, "%a: Timer interrupt is via Sstc extension\n", 
__func__));
+  }
+
   //
   // Make sure the Timer Architectural Protocol is not already installed in 
the system
   //
-- 
2.34.1



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