New week, new review: the memories. Let's begin with the DRAM: - nitpicking: the official names of pins 20 and 47 of U14/U15 are LDM/UDM, not LDQM/UDQM
- the DRAM data sheet [1] says the -5B version (which is what we have) needs Vdd = VddQ = 2.6 +/- 0.1 V for DDR400 operation. If operating at a lower speed, it is content with 2.5 +/- 0.2 V. Do we plan to operate the DRAM in M1r4 at DDR400 speed ? If yes, we should consider raising the voltage. 2.5 V is also supplied to the JTAG board and to the FPGA. The FPGA (I/Os are configured as SSTL2_I for DRAM, TBD for the revision) should have no issue with raising the voltage to 2.6 V. Not sure about the JTAG board. A data point for the termination resistors: Micron recommend to place them halfway between sink and source. (Page 11 of [2], and the theory is on page 4 of [3].) Note sure how picky we have to be given the relatively short distance between FPGA and DRAM. I'd be a bit more concerned about matching trace lengths. [1] http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf [2] http://download.micron.com/pdf/technotes/DDR/tn4614.pdf [3] http://download.micron.com/pdf/technotes/TN4606.pdf I also had a brief look at the NOR and didn't find anything suspicious there. - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
