On 03/20/2012 01:55 AM, Werner Almesberger wrote:
- the DRAM data sheet [1] says the -5B version (which is what we
have) needs Vdd = VddQ = 2.6 ± 0.1 V for DDR400 operation. If
operating at a lower speed, it is content with 2.5 ± 0.2 V.
Do we plan to operate the DRAM in M1r4 at DDR400 speed ? If
yes, we should consider raising the voltage.
No. But the -5B part is needed because it supports CAS latency 3 in
DDR366, which makes it easier to align the data than CAS latency 2.5.
Also, it generally has better timing.
A data point for the termination resistors: Micron recommend to
place them halfway between sink and source. (Page 11 of [2],
and the theory is on page 4 of [3].) Note sure how picky we
have to be given the relatively short distance between FPGA and
DRAM. I'd be a bit more concerned about matching trace lengths.
You can read tons of contradictory information on DDR SDRAM routing...
the point is that the current design works, so don't touch it.
Sébastien
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