S?bastien Bourdeauducq wrote:
> No. But the -5B part is needed because it supports CAS latency 3 in
> DDR366, which makes it easier to align the data than CAS latency
> 2.5. Also, it generally has better timing.
Okay. But at least some of the better timings may only apply to
2.6 V. In the data sheet, I only see characteristics for -5B
at 2.6 V and all the others, but nothing specifically for -5B at
2.5 V.
> You can read tons of contradictory information on DDR SDRAM
> routing... the point is that the current design works, so don't
> touch it.
My main concern is that, now that you're greatly improving
memory performance, parameters close to the limit of where
things can generally be considered to "work" (*) may shift
beyond that limit.
(*) I use careful wording here because there could also be
nasties like one-in-a-billion bit errors.
Other than that, "never change a running system" is fine with
me.
Perhaps we could do some voltage variation tests when the
system with the new memory controller et al. is ready for
deployment. E.g., lower 2.5 V to 2.4 V (means changing R62 to
~2.70 kOhm), then see if things still behave.
- Werner
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