Yann Sionneau <y...@minet.net> schrieb:
>Le 14/07/12 01:42, Michael Walle a écrit : >> Am Montag 09 Juli 2012, 00:52:24 schrieb Yann Sionneau: >>> Hey, >>> >>> Michael Walle asked me to publish a documentation of Milkymist MMU >in >>> order for him to study the feasibility of implementing a model for >this >>> MMU in QEmu. >>> Documenting is always something one needs to do at some point, so >here >>> it is, written very quickly in a small text file. >>> >>> I hope it is clear enough, if you have any question: do not hesitate >to >>> ask me :) >>> This is not a complete documentation, it does not say anything about >>> generated exceptions/TLB miss/page fault etc. >>> >>> Cheers ! >> >> >> I do have some more questions: > >First, MMU "API" is not stable yet, as MMU is not even completed yet. >A few days ago on #milkymist (and here on the mailing list) werner >proposed to use already existing IE CSR to control TLB status >(activated >or not). >It sounded like a good idea because it was using the fact that in >current "vanilla" LM32 implementation IE content is saved upon >exception. > >So I started to change the code to go in that direction and then drop >the use of TLBCTRL CSR (at least to enable/disable TLBs) in favour or >using IE CSR. > >But then on #milkymist I saw a few arguments against using IE, so I am >not that sure anymore. > >I think we need to talk about that a little bit more before continuing >to implement (or to do a MMU model in Qemu). > >I don't want to waste my time and I even more don't want to waste your >time in changes :) the qemu model is fairly complete now. at least a first version. >> - are there one or two addition exception vectors? one for both ITLB >and >> DTLB? > >For now the current MMU implementation uses one exception vector for >each TLB. > >As can be seen there : > >- >https://github.com/fallen/milkymist-mmu/blob/mmu-bios/software/mmu-bios/crt0.S#L112 >- >https://github.com/fallen/milkymist-mmu/blob/mmu-bios/software/mmu-bios/tlb_miss_handler.c > >> - where do i read back the bad address? Looking at the source i >guess i could >> read it from any of the CSRs? Is there a preferred one? > >You can read faulty address for DTLB miss from DTLBMA CSR >You can read faulty address for ITLB miss from ITLBMA CSR > >> - you are what is I/DTLBMA? tlb miss address? > >These CSR permit to read the latest address which generated a TLB miss. >DTLBMA CSR id == TLBVADDR CSR id >ITLBMA CSR id == TLBPADDR CSR id > >as can be seen there : >https://github.com/fallen/lm32-binutils-mmu/commit/95e32bfe197b19067b72ff22845f206821d60399 > >reading from DTLBMA or TLBVADDR gives the same thing >reading from ITLBMA or TLBPADDR gives the same thing > >Therefore reading and writing form/to TLBVADDR does not touch the same >"FPGA internal register". >In other words, you cannot read back what you've written to the CSR. >It is the same thing for TLBPADDR. > >> - you're saying that it simplifies the hardware if the lowest bit >selects >> between DTLB and ITLB for the TLB{P|V}ADDR registers? What is the >> restriction here? > >It simplifies the hardware because I use two CSR ids instead of 4. >Each CSR has two purposes instead of just one. > >I just noticed there are wholes in CSR id definitions in >https://github.com/fallen/milkymist-mmu/blob/mmu/boards/milkymist-one/rtl/lm32_include.v > >We have a few unused CSR ids : 0xb 0xc 0xd 0x14 0x15 0x16 0x17 0x1f > >We could use those :o > >You're saying there are seperate registers for both TLBs. >> Would it be possible to update both, the ITLB and the DTLB one, at >the same >> time when writing for example to TLBPADDR? > >We could use two bits instead of just one and therefore if value >written >to CSR reg ends with 2'b11 it could mean "write to both TLBs". > >2'b10 => ITLB only >2'b01 => DTLB only >2'b00 => NoOp ? >2'b11 => both ITLB and DTLB > >It is not implemented like this ATM but it could be, and it would not >be >hard to implement :) the question is why do we need two or why do we need to update them seperately? in my qemu model there is only one vaddr/paddr Register. Which tlb table youre updating can be specified by The tlbcrtl Register. So if youre seperating them to simplify the hw, can they be updated always together. > >> - i can't find the ITLB handling, isn't it checked in yet? >> > >ITLB is quite experimental for now, I think I made a major design error >in both hardware and software for ITLB. I will try to focus on fixing >those in the following weeks. > >For now ITLB stuff are only committed in "simulation" >branches/repositories, not in "FPGA" stuff. Because it works fine in >ISim and crashes a lot in FPGA ;) > >For ITLB stuff see : > >- Migen generated SoC for ISim simulation - with DTLB *and* ITLB - : >https://github.com/fallen/milkymist-mmu-simulation >- software (bios, libhal, libbase) to run in ISim environment : >https://github.com/fallen/milkymist-mmu/tree/mmu-bios/software ( branch >mmu-bios of the git repo, not mmu branch ) > >The BIOS I used for my tests on real FPGA (on M1) is there : >https://github.com/fallen/milkymist-mmu/tree/mmu/software/bios (mmu >branch) > >It only contains DTLB stuff, nothing about ITLB. > >I hope all of this makes sense :) > >Thanks ! _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
